LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 210

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Table 9-14. PFU based Distributed Single port RAM Port Definitions
Users have an option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 8-35 and 8-36 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM)
with these options.
Figure 9-53. PFU Based Distributed Single Port RAM Timing Waveform - Without Output Registers
ClockEn
Address
Clock
Data
Clock
ClockEn
Reset
WE
Address
Data
Q
WE
Q
Generated Module
Port Name in
t
t
SUWREN_PFU
SUADDR_PFU
t
SUDATA_PFU
Data_0
Add_0
Invalid Data
CK
-
-
WRE
AD[3:0]
DI[1:0]
DO[1:0]
Port Name in the EBR
t
t
HADDR_PFU
HDATA_PFU
Block Primitive
Data_1
Add_1
t
HWREN_PFU
t
CORAM_PFU
9-45
Clock
Clock Enable
Reset
Write Enable
Address
Data In
Data Out
Add_0
Description
LatticeECP/EC and LatticeXP Devices
Data_0
Add_1
Data_1
Rising Clock Edge
Active High
Active High
Active High
—
—
—
Memory Usage Guide
Active State
Add_2
Data_2