LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 196

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 9-33. FIFO Without Output Registers, Start of Data Write Cycle
The WrEn signal has to be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin
and Full and Almost full are low.
When the first data gets written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer
empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag gets de-asserted when the 3rd address location gets filled.
Now let is assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full
Flags are asserted. Figure 9-34 shows the behavior of these flags. In this figure we assume that FIFO depth is ‘N’.
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-31
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide