LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 208
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LFXP10C-3F388I
Manufacturer Part Number
LFXP10C-3F388I
Description
FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
Manufacturer
Lattice
Specifications of LFXP10C-3F388I
Package
388FBGA
Family Name
LatticeXP
Device Logic Units
10000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
244
Ram Bits
221184
Re-programmability Support
Yes
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP10C-3F388I
Manufacturer:
LATTICE
Quantity:
176
Company:
Part Number:
LFXP10C-3F388I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 9-49. FIFO_DC With Output Registers, End of Data Read Cycle
Finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle (as
compared to the non-pipelined FIFO_DC), and the RdEn should be high also during that clock cycle. Otherwise the
data takes an extra clock cycle when the RdEn is goes true.
Figure 9-50. FIFO_DC With Output Registers and RdEn on Output Registers
RPReset
RPReset
WrClock
RdClock
WrClock
RdClock
Almost
Almost
Almost
Almost
Empty
Empty
Empty
Empty
Reset
Reset
WrEn
RdEn
WrEn
RdEn
Data
Data
Full
Full
Full
Full
Q
Q
Data_N-4
Data_N-3
Invalid Q
Data_N-2
9-43
Invalid Data
Invalid Data
Data_1
Data_1
LatticeECP/EC and LatticeXP Devices
Data_N
Data_2
Data_3
Memory Usage Guide
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