LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 168

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 9-3. Simplified Block Diagram, LatticeXP Device (Top Level)
Utilizing IPexpress
Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules will be con-
structed using one or more memory primitives along with general purpose routing and LUTs as required. The avail-
able modules are:
IPexpress Flow
For generating any of these memories, create (or open) a project for the LatticeECP/EC or LatticeXP devices.
From the Project Navigator, select Tools > IPexpress. Alternatively, users can also click on the button in the tool-
bar when the LatticeECP/EC and LatticeXP devices are targeted in the project.
This opens the IPexpress window as shown in Figure 9-4.
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
Non-volatile Memory
• Single Port RAM (RAM_DQ) – EBR based
• Dual PORT RAM (RAM_DP_TRUE) – EBR based
• Pseudo Dual Port RAM (RAM_DP) – EBR based
• Read Only Memory (ROM) – EBR Based
• First In First Out Memory (FIFO and FIFO_DC) – EBR Based
• Distributed Single Port RAM (Distributed_SPRAM) – PFU based
• Distributed Dual Port RAM (Distributed_DPRAM) – PFU based
• Distributed ROM (Distributed_ROM) – PFU/PFF based
Programmable
Functional Unit (PFU)
Programmable I/O Cell
(PIC) includes sysIO
Interface
9-3
LatticeECP/EC and LatticeXP Devices
Memory Usage Guide
JTAG Port
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
PFF (PFU without
RAM)