LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 215

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 9-60. PFU-based Distributed ROM (Sync_ROM) for LatticeECP/EC and LatticeXP Devices
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for the memory are included in Table 9-16. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 9-16. PFU-based Distributed ROM Port Definitions
Users have the option of enabling the output registers for Distributed ROM (Distributed_ROM). Figures 8-43 and 8-
44 show the internal timing waveforms for the Distributed ROM with these options.
Figure 9-61. PFU Based ROM Timing Waveform – without Output Registers
Address
OutClock
OutClockEn
Reset
Q
Port Name in Generated
Module
Address
Q
AD[3:0]
—
—
—
DO
Invalid Data
Port Name in the EBR
t
SUADDR_PFU
Block Primitive
AD[3:0]
Add_0
t
HADDR_PFU
t
CORAM_PFU
9-50
PFU
Address
Out Clock
Out Clock Enable
Reset
Data Out
Data_0
Add_1
Description
LatticeECP/EC and LatticeXP Devices
DO
Data_1
Add_2
—
Rising Clock Edge
Active High
Active High
—
Memory Usage Guide
Active State
Data_2