LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 178

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
True Dual Port RAM (RAM_DP_TRUE) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as True-Dual Port RAM or
RAM_DP_TRUE. IPexpress allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size
as per design requirements.
IPexpress generates the memory module as shown in Figure 9-15.
Figure 9-15. True Dual Port Memory Module Generated by IPexpress
The generated module makes use of the RAM_DP_TRUE primitive. For memory sizes smaller than one EBR
block, the module will be created in one EBR block. In cases where the specified memory is larger than one EBR
block, multiple EBR blocks can be cascaded, in depth or width (as required to create these sizes).
The basic memory primitive for the LatticeECP/EC and LatticeXP devices, RAM_DP_TRUE, is shown in Figure 9-
16.
Figure 9-16. True Dual Port RAM Primitive or RAM_DP_TRUE for LatticeECP/EC and LatticeXP Devices
In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
ADA[x:0]
WrAddressA
DOA[y:0]
CSA[2:0]
DIA[y:0]
ClockEnA
RSTA
CLKA
ResetA
WEA
ClockA
CEA
DataA
WEA
QA
Dual Port Memory
EBR-based True
RAM_DP_TRUE
9-13
EBR
LatticeECP/EC and LatticeXP Devices
ClockB
ClockEnB
ResetB
WEB
WrAddressB
DataB
QB
CLKB
CEB
RSTB
WEB
CSB[2:0]
DOB[y:0]
ADB[x:0]
DIB[y:0]
Memory Usage Guide