LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 250

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Verilog Example
module ddrin (rst, ddrclk, ddrdata, datap, datan)/*synthesis syn_useioff = 0*/;
// Inputs
input
input
input
// Outputs
output
reg [7:0] pos0/*synthesis syn_keep=1*/;
reg [7:0] pos1/*synthesis syn_keep=1*/;
reg [7:0] neg0/*synthesis syn_keep=1*/;
reg [7:0] datap, datan/*synthesis syn_keep=1*/;
//PLL signals
wire ddrclk0;
wire ddrclk90;
pll I0 (.CLK(ddrclk), .RESET(rst), .CLKOP(ddrclk0), .CLKOS(ddrclk90), .LOCK(clklock));
always @ ( posedge ddrclk90)
begin
end
always@ (negedge ddrclk90)
begin
end
always @ (posedge ddrclk90)
begin
if (rst)
begin
pos0 <= 0;
end
else
begin
end
if (rst)
begin
end
else
begin
end
if (rst)
begin
end
else
begin
end
pos0 <= ddrdata;
neg0<=0;
pos1<=0;
neg0<=ddrdata;
pos1<=pos0;
datap<= 0;
datan<= 0;
datap<= pos1;
datan<= neg0;
[7:0]
[7:0]
rst;
ddrclk;
ddrdata;
datap, datan;
10-31
LatticeECP/EC and LatticeXP
DDR Usage Guide