LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 214

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figure 9-58. PFU Based Distributed Dual Port RAM Timing Waveform – With Output Registers
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-59 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-59. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. The basic Distributed Dual Port RAM
primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-60.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Reset
Data
WE
Q
t
t
t
SUWREN_PFU
SUWREN_PFU
t
SUADDR_PFU
SUDATA_PFU
Data_0
Add_0
OutClockEn
OutClock
t
t
HADDR_PFU
HDATA_PFU
Address
t
HWREN_PFU
Reset
Invalid Data
Data_1
Add_1
9-49
Distributed ROM
PFU-based
t
SUCE_PFU
Add_0
LatticeECP/EC and LatticeXP Devices
t
HWREN_PFU
t
CORAM_PFU
Q
Data_0
Add_1
Memory Usage Guide
Data_1
t
HCE_PFU