LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 349

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
The above information was specified under the following environmental conditions:
The goal of this exercise is to compute the following device I/O constraints:
The only parameter which can be obtained from the above is the device junction temperature:
The required constraints can be computed as follows:
1. Input setup specification
2. Input hold specification
3. Output maximum propagation delay requirement
4. Output minimum propagation delay requirement
5. Output loading
The preference file to use for this example is shown in Figure 17-3. For more preference language syntax and
examples, refer to the Constraints & Preferences section of the ispLEVER on-line help system.
• Board trace AC loading (Cbac): 60 pf.
• Board trace parasitic capacitance (Cb): 5 pf.
• Port controller input capacitance (Cp) :9 pf.
• FPGA device input capacitance (Co): 9 pf.
• Maximum ambient temperature (Ta): 70 (C.
• Estimated Power Consumption (Q): 2 W.
• 680 PBGAM Package Thermal resistance (j) at 0 feet per minute (fpm) airflow: 13.4 °C/W.
1. Input setup specification.
2. Input hold specification.
3. Maximum output propagation delay.
4. Minimum output propagation delay.
5. Output loading.
6. Temperature.
Tj = j * Q - Ta
= 13.4 * 2 + 70
= 96.8 °C
= P - PDMAXp - PDMAXb - Tskew
= 30 - 18 - 2 - 1
= 9 ns
= PDMINp + PDMINb - Tskew
= 3 + 1 - 1
= 3 ns
= P - TSp - PDMAXb - Tskew
= 30 - 5 - 6 - 1
= 18 ns
= Thp - PDMINb + Tskew
= 3 - 1 + 1
= 3 ns
= Cbac + Cb + Cp
= 60 + 5 + 9
= 74 pf
17-5
Lattice Semiconductor FPGA
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