LFXP10C-3F388I Lattice, LFXP10C-3F388I Datasheet - Page 331

• Manufacturer Part Number: LFXP10C-3F388I
• Description: FPGA LatticeXP Family 10000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
• Manufacturer: Lattice

Specifications of LFXP10C-3F388I

• Package: 388FBGA
• Family Name: LatticeXP
• Device Logic Units: 10000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 244
• Ram Bits: 221184
• Re-programmability Support: Yes
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
attributes in the source code or through the tool’s Graphical User Interface (GUI). Each synthesis tool has its own
synthesis attributes and syntax for choosing the encoding styles. Refer to the synthesis tools documentation for
details about attributes syntax and values.
The following syntax defines an enumeration type in VHDL:
Here is a VHDL example of enumeration states:
The following are examples of Synplify
Synplify:
LeonardoSpectrum:
In Verilog, one must provide explicit state values for states. This can be done by using the bit pattern (e.g., 3'b001),
or by defining a parameter and using it as the case item. The latter method is preferable. The following is an exam-
ple using parameter for state values.
The attributes in the source code override the default encoding style assigned during synthesis. Since Verilog does
not have predefined attributes for synthesis, attributes are usually attached to the appropriate objects in the source
code as comments. The attributes and their values are case sensitive and usually appear in lower case. The follow-
ing examples use attributes in Verilog source code to specify state machine encoding style.
Synplify:
In LeonardoSpectrum, it is recommended to set the state machine variable to an enumeration type with enum
pragma. Once this is set in the source code, encoding schemes can be selected in the LeonardoSpectrum GUI.
LeonardoSpectrum:
In general, synthesis tools will select the optimal encoding style that takes into account the target device architec-
ture and size of the decode logic. One can always apply synthesis attributes to override the default encoding style
if necessary.
type type_name is (state1_name,state2_name,......,stateN_name)
type STATE_TYPE is (S0,S1,S2,S3,S4);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
attribute syn_encoding : string;
attribute syn_encoding of <signal_name> : type is "value ";
-- The syn_encoding attribute has 4 values : sequential, onehot, gray and safe.
-- Declare TYPE_ENCODING_STYLE attribute
-- Not needed if the exemplar_1164 package is used
type encoding_style is (BINARY, ONEHOT, GRAY, RANDOM, AUTO);
attribute TYPE_ENCODING_STYLE : encoding_style;
...
attribute TYPE_ENCODING_STYLE of <typename> : type is ONEHOT;
Parameter state1 = 2'h1, state2 = 2'h2;
...
current_state = state2; // setting current state to 2'h2
Reg[2:0] state; /* synthesis syn_encoding = "value" */;
// The syn_encoding attribute has 4 values : sequential, onehot, gray and safe.
Parameter /* exemplar enum <type_name> */ s0 = 0, s1 = 1, s2 = 2, s3 = 3, S4 = 4;
Reg [2:0] /* exemplar enum <type_name> */ present_state, next_state ;
®
and LeonardoSpectrum
13-4
®
VHDL synthesis attributes.
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs