DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet
DSPB56366AG120
Specifications of DSPB56366AG120
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DSPB56366AG120 Summary of contents
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... MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved. Document Number: DSP56366 Rev ...
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... EXTERNAL 18 XAB ADDRESS PAB BUS ADDRESS DAB SWITCH DRAM & SRAM BUS 10 INTERFACE & CONTROL I - CACHE EXTERNAL 24 DATA BUS SWITCH DATA POWER MNGMNT DATA ALU 24X24 + 56 -> 56-BIT MAC 4 TWO 56-BIT JTAG ACCUMULATORS OnCE™ BARREL SHIFTER 24 BITS BUS Freescale Semiconductor ...
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... Serial Audio Interface I(ESAI_1 receivers and transmitters, master or slave. I Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks) Freescale Semiconductor i : i=0 to 7). Reduces clock noise. DSP56366 Technical Data, Rev. 3.1 ...
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... Detailed description of memory, peripherals, and interfaces Brief description of the chip Electrical and timing specifications; pin and package descriptions Input Output Buffer Information Specification. DSP56366 Technical Data, Rev. 3.1 Order Number DSP56300FM DSP56366UM DSP56366P DSP56366 For software or simulation models, contact sales www.freescale.com. Freescale Semiconductor ...
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... Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 4 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 5 Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Freescale Semiconductor 2-1. 1 Port A 2 ...
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... HACK/HRRQ [PB15] VCCH GNDH SCKT[PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] SCKT_1[PE3] FS T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ Freescale Semiconductor ...
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... Address Bus Ground—GND A connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND Freescale Semiconductor Table 2-2 Power Inputs Description is V dedicated for PLL use. The voltage should be well-regulated and the input isolated power for the internal processing logic ...
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... PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. This input cannot tolerate 5 V. DSP56366 Technical Data, Rev. 3.1 connections CCP , GND, or left floating. CC Freescale Semiconductor ...
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... Output Tri-stated WR Output Tri-stated Freescale Semiconductor Table 2-5 External Address Bus Signals Signal Description Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed ...
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... BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset deasserted and the arbitration is reset to the bus slave state. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Ignored Input Bus Grant— active-low input asserted by an external bus BB Input/Output Input Freescale Semiconductor Signal Description arbitration circuit when the DSP56366 becomes the next bus master. When BG is asserted, the DSP56366 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle ...
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... RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... HA8 Input disconnected PB9 Input, output, or disconnected disconnected Freescale Semiconductor Table 2-9 Host Interface Reset GPIO Host Data—When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional, tri-state data bus. GPIO Host Address/Data— ...
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... Host Chip Select—When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. DSP56366 Technical Data, Rev. 3.1 Signal Description Freescale Semiconductor ...
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... Output HRRQ disconnected PB15 Input, output, or disconnected disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) Reset GPIO Host Address 10—When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. GPIO Port B 13— ...
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... SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. DSP56366 Technical Data, Rev. 3 bus transactions in the I through a pull- mode, SDA is a Schmitt-trigger input when 2 C transactions. The data Freescale Semiconductor 2 C mode mode. ...
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... Input SS Input Tri-stated HA2 Input HREQ Input or Tri-stated Output Freescale Semiconductor Signal Description Slave Address 0—This signal uses a Schmitt-trigger input when configured for 2 2 the I C mode. When configured for I C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I This signal is tri-stated during hardware, software, and individual reset ...
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... Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... SDI0 Input GPIO disconnected Freescale Semiconductor Signal Description Frame Sync for Transmitter—This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only ...
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... Port C 9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Input, output, or GPIO PE11 disconnected disconnected Freescale Semiconductor Signal Description Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1. Port C 10—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected ...
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... When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. DSP56366 Technical Data, Rev. 3.1 Signal Description Freescale Semiconductor ...
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... SDI1_1 Input disconnected PE7 Input, output, or disconnected disconnected Freescale Semiconductor Reset GPIO Port E 0—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 5 V. GPIO Transmitter Serial Clock_1— ...
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... If TIO0 is not being used recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Signal Description Signal Description Freescale Semiconductor ...
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... TDO Output Tri-stated TMS Input Input Freescale Semiconductor Table 2-15 JTAG/OnCE Interface Signal Description Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input tolerant. Test Data Input—TDI is a test data serial input signal used for test instructions and data ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Rating Supply Voltage All input voltages excluding “5 V tolerant” inputs 3 All “5 V tolerant” input voltages Current drain per pin excluding V CC Freescale Semiconductor CAUTION ). The suggested value for a pullup or pulldown CC NOTE Table 3-1 Maximum Ratings Symbol V CC ...
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... J L Table 3-2 Thermal Characteristics 1, 2 Natural Convection 3 4 Natural Convection DSP56366 Technical Data, Rev. 3 Value − +110 − +125 Symbol LQFP Value Unit or θ ° C/W θ θ ° C/W θJC JC Ψ ° 2.0 C/W JT Freescale Semiconductor Unit ° C ° C ...
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... Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins. 3 Driving EXTAL to the low V or the high V IHX power consumption, the minimum V 0.1 × Periodically sampled and not 100% tested. 5 This characteristic does not apply to PCAP. Freescale Semiconductor Table 3-3 DC Electrical Characteristics Symbol IHP /SHI (only SDO4_1) (SPI V ...
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... Max — Ef/2 — ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF × PDF × DF/MF — C Freescale Semiconductor ...
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... With PLL disabled (46.7%–53.3% duty cycle • With PLL enabled (42.5%–57.5% duty cycle EXTAL input low • With PLL disabled (46.7%–53.3% duty cycle • With PLL enabled (42.5%–57.5% duty cycle Freescale Semiconductor Table 3-4 Internal Clocks Symbol Min T — — ...
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... Expression Min Max — — 26.0 50 × ET 416.7 C 1000 × ET 8.3 C 2.5 × T 20.8 C 3.25 × 2.0 29.1 C 20. 7.50 — 176.2 C 30.0 Freescale Semiconductor Max ∞ 273.1 μs ∞ 8.53 μs Unit MHz pF Unit ns — ns μs — — ns — — ns ...
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... PLL is not active during Stop (PCTL Bit and Stop delay is enabled (OMR Bit • PLL is not active during Stop (PCTL Bit and Stop delay is not enabled (OMR Bit • PLL is active during Stop (PCTL Bit (implies no Stop delay) Freescale Semiconductor Expression 4.25 × T 7.25 × × T 3.75 × × ...
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... DSP56366 Technical Data, Rev. 3.1 1 (continued) Min Max 12T — 100 — 66 — 66.7 C 12T — 100 — 50 — — 25 2.0 37.4 — valid, and the EXTAL input is active and Freescale Semiconductor Unit ...
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... A0–A17 A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI Freescale Semiconductor 9 Reset Value Figure 3-2 Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing DSP56366 Technical Data, Rev ...
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... RESET MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-6 Recovery from Stop State Using IRQA 3- Figure 3-5 Operating Mode Select Timing 24 25 DSP56366 Technical Data, Rev. 3.1 AA0463 IRQA, IRQB IRQD, NMI V IL AA0465 First Instruction Fetch AA0466 Freescale Semiconductor ...
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... Figure 3-8 External Memory Access (DMA Source) Timing 3.10 External Memory Expansion Port (Port A) 3.10.1 SRAM Timing Table 3-8 SRAM Read and Write Accesses No. Characteristics 100 Address valid and AA assertion pulse width Freescale Semiconductor 26 25 DMA Source Address 29 First Interrupt Instruction Execution Symbol Expression ( × ...
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... C − 4.0 14.7 — C [WS ≥ 8] − 7.0 — 7.6 C [WS ≥ 1] − 7.0 — 3.4 C [WS ≥ 1] 0.0 — − 4.0 10.6 — C [WS ≥ 1] − 3.0 3.2 — C [WS ≥ 1] Freescale Semiconductor Unit ...
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... Characteristics 109 Data hold time from WR deassertion 110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time Freescale Semiconductor 1 Symbol Expression 0.25 × ≤ WS ≤ 3] 1.25 × ≤ WS ≤ 7] 2.25 × T [WS ≥ 8] 0.75 × ...
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... Unit − 4.0 0.2 — C 6.3 — − 4.0 16.8 — C − 4.0 25.2 — C − 4.0 0.2 — C −4.0 6.4 — C − 2.0 0.1 — C − 2.0 8.4 — C − 2.0 16.7 — 2.0 4.1 — C 0.0 — Freescale Semiconductor ...
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... A0–A17 AA0–AA2 D0–D23 A0–A17 AA0–AA2 D0–D23 Freescale Semiconductor 100 113 116 115 105 104 119 Figure 3-9 SRAM Read Access 100 107 101 102 114 108 Figure 3-10 SRAM Write Access DSP56366 Technical Data, Rev. 3.1 117 106 118 ...
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... Notes This figure should be use for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait States 4 Wait States DSP56366 Technical Data, Rev. 3.1 Chip Frequency (MHz) AA0472 Freescale Semiconductor ...
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... WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion h 146 WR assertion pulse widt 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (Write) Freescale Semiconductor Symbol Expression 2 × 1.25 × − 7 CAC C 1.5 × ...
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... Freescale Semiconductor Unit for C Unit ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56366. 4 There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Freescale Semiconductor Symbol Expression 6 t CRP 2.0 × 3.5 × ...
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... C 0.75 × T − 4.0 3.5 — 2.25 × T − 4.2 18.3 — 3.5 × T − 4.5 30.5 — 3.75 × T − 4.3 33.2 — 3.25 × T − 4.3 28.2 — 0.5 × T − 4.0 1.0 — Freescale Semiconductor ...
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... Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS assertion • BRW[1: • BRW[1: • BRW[1: • BRW[1: 139 CAS deassertion pulse width Freescale Semiconductor 6 Symbol t 5 DSP56366 Technical Data, Rev. 3 (continued) 4 Symbol Expression Min Max 2.5 × ...
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... DH C 1.25 × T − 4.3 6.1 — C 4.5 × T − 4.0 33.5 — C 3.25 × T − 7.0 — 20 0.0 — GZ 0.75 × T − 0.3 5.9 — C 0.25 × T — 2 equals 3 × and not t . OFF GZ Freescale Semiconductor Unit for C ...
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... RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-12 DRAM Page Mode Write Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56366 Technical Data, Rev. 3.1 ...
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... Figure 3-13 DRAM Page Mode Read Accesses 3-24 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56366 Technical Data, Rev. 3.1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 Freescale Semiconductor ...
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... Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion Freescale Semiconductor and detailed timings see the following tables. 120 66 80 100 ...
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... Freescale Semiconductor Unit ...
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... RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid Freescale Semiconductor 3 Symbol Expression 4.5 × ROH C 4 × ...
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... C − 4.0 124.8 — 102.3 − 7.5 — 106.1 — − 6.5 — — — 87.3 Freescale Semiconductor Unit — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ...
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... RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion Freescale Semiconductor 3 Symbol Expression 4 t 0.0 GZ 0.75 × T 0.25 × ...
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... T − 4.0 11.0 — C 2.75 × T − 4.0 23.5 — C 11.5 × T − 4.0 111.0 — × T − 7.0 — 93.0 C 0.0 — 0.75 × T − 0.3 7.2 — C 0.25 × T — 2.5 C and not t . OFF GZ Freescale Semiconductor Unit ...
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... Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 4 178 CAS deassertion to WR assertion 5 179 RAS deassertion to WR assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion Freescale Semiconductor 3 Symbol RAC t CAC OFF RAS t RSH ...
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... T − 4.0 8.5 — C 4.75 × T − 4.0 35.6 — C 15.5 × T − 4.0 125.2 — × T − 5.7 — 111.0 C 0.0 — 0.75 × T − 0.3 5.9 — C 0.25 × T — 2.1 C and not t . OFF GZ Freescale Semiconductor Unit ...
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... RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-15 DRAM Out-of-Page Read Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56366 Technical Data, Rev. 3.1 ...
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... Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56366 Technical Data, Rev. 3.1 162 174 195 AA0477 Freescale Semiconductor ...
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... Notes: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode 2. If Asynchronous Arbitration mode is active, none of the timings order to guarantee timings 250, and 251 recommended to assert same bus non overlap manner as shown in Freescale Semiconductor 157 163 162 165 189 ...
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... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided. 3-36 250 250+251 DSP56366 Technical Data, Rev. 3.1 251 Freescale Semiconductor ...
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... Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion 330 HCS assertion to read data strobe deassertion 331 HCS assertion to write data strobe deassertion 332 HCS assertion to output data valid Freescale Semiconductor 3 Characteristics after “Last Data Register” reads 7 ...
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... T 8.3 — × T 16.7 — C — — 19.1 — — 300 × 19.1 35.8 — C 1.5 × 19.1 31.6 — C 0.0 — — — 20.2 — — 300.0 Freescale Semiconductor Unit ...
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... HD7–HD0 HOREQ Figure 3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram HA0–HA2 HCS HRD, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 317 327 329 326 336 337 333 330 317 318 ...
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... HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus 3-40 336 331 320 321 324 340 341 DSP56366 Technical Data, Rev. 3.1 337 333 325 339 AA0485 Freescale Semiconductor ...
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... HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-23 Read Timing Diagram, Multiplexed Bus Freescale Semiconductor 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56366 Technical Data, Rev. 3.1 318 319 ...
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... Figure 3-25 Host DMA Write Timing Diagram 3-42 336 323 320 334 324 335 Data Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56366 Technical Data, Rev. 3.1 321 325 339 AA0487 Freescale Semiconductor ...
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... Serial Host Interface SPI Protocol Timing Table 3-19 Serial Host Interface SPI Protocol Timing 1 No. Characteristics 140 Tolerable spike width on clock or data in 141 Minimum serial clock cycle = t 142 Serial clock high period Freescale Semiconductor HOREQ (Output) 343 342 317 HACK RXH (Input) Read 327 ...
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... — — — — — — 102 102 — 189 189 — — 11.7 — 31.7 — C 2.5×T +10 30.8 — C 2.5×T +30 50.8 — C 2.5×T +50 70.8 — — 9 — 9 Freescale Semiconductor Unit ...
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... First SCK edge to HREQ in not asserted (HREQ in hold time 3.16 V ± 0. –40°C to +110° Periodically sampled, not 100% tested Freescale Semiconductor Filter Mode Mode Master/Slave Bypassed Narrow Wide Master/Slave Bypassed Narrow Wide Slave — ...
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... HREQ (Input) 3-46 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 163 Figure 3-27 SPI Master Timing (CPHA = 0) DSP56366 Technical Data, Rev. 3.1 141 144 141 144 149 LSB Valid 153 LSB AA0271 Freescale Semiconductor ...
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... SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-28 SPI Master Timing (CPHA = 1) DSP56366 Technical Data, Rev. 3.1 ...
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... MSB 148 149 MSB Valid 157 Figure 3-29 SPI Slave Timing (CPHA = 0) DSP56366 Technical Data, Rev. 3.1 141 147 144 160 141 144 151 LSB 149 LSB Valid 159 AA0273 Freescale Semiconductor ...
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... SS (Input) SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 150 MISO (Output) MOSI (Input) HREQ (Output) Freescale Semiconductor 143 142 144 142 144 143 152 152 MSB 148 149 MSB Valid 157 Figure 3-30 SPI Slave Timing (CPHA = 1) DSP56366 Technical Data, Rev. 3.1 ...
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... C 300 b — 100 — — 0.0 0.9 — 28.5 — — 39.7 — — 61.0 — 3.4 — 0.9 — 0.6 — — 0.0 — Freescale Semiconductor Unit kHz μs μs μs μs μs μ μs MHz μs μs ns ...
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... J 2 Pull-up resistor: R (min) = 1.5 kOhm P 3 Capacitive load: C (max) = 400 recommended to enable the wide filters when operating in the recommended to enable the narrow filters when operating in the I Freescale Semiconductor 2 C Protocol Timing (continued) Standard 4 Symbol/ Mode Expression Min Max T NG;RQO × ...
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... DSP56366 Technical Data, Rev. 3.1 ( × HRS – and the filters selected should be chosen Table 3-21. × 45ns + R C × 135ns + R C × 223ns + environment – = 8756ns × – = 64.67 Freescale Semiconductor ...
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... The resulting T will be CCP CCP CCP T I 173 SCL 177 172 SDA Stop Start 174 188 HREQ Freescale Semiconductor [ × × × HDM 7 × × × = 8.33ns × × × 8.33ns CCP 171 176 175 180 178 179 MSB LSB 186 ...
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... Freescale Semiconductor ...
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... FST input (bl, wr) setup time before TXC 6 falling edge 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to transmitter #0 drive enable assertion Freescale Semiconductor Symbol Expression — — — — — — — — ...
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... Symbol Expression — — — — — — — — — — — — DSP56366 Technical Data, Rev. 3.1 4 Min Max Condition Unit 2.0 — 21.0 — 4.0 — 0.0 — — 32 — 18 40.0 — ns — 27.5 ns — 27.5 ns Freescale Semiconductor ...
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... FST (Bit) In FST (Word) In Flags Out Notes In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Freescale Semiconductor 430 432 446 447 450 ...
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... SCKT(output) 3-58 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-33 ESAI Receiver Timing 463 464 Figure 3-34 ESAI HCKT Timing DSP56366 Technical Data, Rev. 3.1 438 440 Last Bit 443 445 AA0491 Freescale Semiconductor ...
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... Note: In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56366 internal clock frequency. For example, if the DSP56366 is running at 120 MHz internally, the ACI frequency should be less than 60 MHz. ACI 223 ADO Figure 3-36 Digital Audio Transmitter Timing Freescale Semiconductor 463 465 Figure 3-35 ESAI HCKR Timing Expression × ...
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... Table 3-25 GPIO Timing 1 Expression 6.75 × DSP56366 Technical Data, Rev. 3.1 120 MHz Unit Min Max 18.7 — ns 18.7 — ns AA0492 Min Max — 32.8 4.8 — 10.2 — 1.8 — -1.8 54.5 — C — — 13 — — 13 Freescale Semiconductor Unit ...
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... Boundary scan input data hold time 506 TCK low to output data valid 507 TCK low to output high impedance 508 TMS, TDI data setup time Freescale Semiconductor 492 493 Valid 494 495 496 Figure 3-38 GPIO Timing Table 3-26 JTAG Timing Characteristics × ...
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... Characteristics = 501 502 VM VIL 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid DSP56366 Technical Data, Rev. 3.1 All frequencies Min Max 25.0 — 0.0 44.0 0.0 44.0 502 VM 503 AA0496 VIH 505 AA0497 Freescale Semiconductor Unit ...
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... VIL (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-41 Test Access Port Timing Diagram Freescale Semiconductor 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56366 Technical Data, Rev. 3.1 VIH 509 AA0498 ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Table 4-2 show the pin/name assignments for the packages. 4.1.1 LQFP Package Description Top view of the 144-pin LQFP package is shown in shown in Figure 4-2. Freescale Semiconductor Section 2, “Signal/Connection Figure 4-1 with its pin-outs. The package drawing is DSP56366 Technical Data, Rev. 3.1 4-1 ...
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... Figure 4-1 144-pin package DSP56366 Technical Data, Rev. 3.1 108 D6 107 D5 106 D4 105 D3 104 GNDD 103 VCCD 102 D2 101 D1 100 D0 99 A17 98 A16 97 A15 96 GNDA 95 VCCQH 94 A14 93 A13 92 A12 91 VCCQL 90 GNDQ 89 A11 88 A10 87 GNDA 86 VCCA GNDA 80 VCCA GNDA 74 VCCA 73 A1 Freescale Semiconductor ...
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... GNDD D2 102 GNDD D3 105 GNDH D4 106 GNDP D5 107 GNDQ D6 108 GNDQ D7 109 GNDQ D8 110 GNDQ Freescale Semiconductor Table 4-1 Signal Identification by Name Pin No. Signal Name Pin No. 113 GNDS 114 GNDS 26 115 HA8/HA1 32 116 HA9/HA2 31 117 HACK/HRRQ 23 118 HAD0 43 121 HAD1 ...
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... VCCD A14 130 GNDD VCCQH 131 D21 GNDA 132 D22 A15 133 D23 A16 134 MODD/IRQD# A17 135 MODC/IRQC# D0 136 MODB/IRQB# D1 137 MODA/IRQA# D2 138 SDO4_1/SDI1_1 VCCD 139 TDO GNDD 140 TDI D3 141 TCK D4 142 TMS D5 143 MOSI/HA0 D6 144 MISO/SDA Freescale Semiconductor ...
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... LQFP Package Mechanical Drawing Figure 4-2 DSP56366 144-pin LQFP Package Freescale Semiconductor CASE 918-03 DSP56366 Technical Data, Rev. 3.1 4-5 ...
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... DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. Freescale Semiconductor , in °C can be obtained from the following equation × ...
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... TDI, TCK). 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pullup or pulldown resistor CC power source to GND. CC and GND circuits. CC DSP56366 Technical Data, Rev. 3.1 – has been defined JT pin on the DSP and from CC and GND. CC Freescale Semiconductor and CC ...
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... DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. Freescale Semiconductor CCP × ...
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... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5-4 ⁄ MHz = – I typF2 typF1 NOTE DSP56366 Technical Data, Rev. 3.1 ) ⁄ Freescale Semiconductor ...
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... HC bit is cleared. • Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make Freescale Semiconductor DSP56366 Technical Data, Rev. 3.1 5-5 ...
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... HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. 5-6 DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Ordering Information Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering DSP Audio products, refer to the current SG1004, DSP Selector Guide, at http://www.freescale.com Freescale Semiconductor DSP56366 Technical Data, Rev. 3.1 6-1 ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... PLOAD_LOOP ; ; Load the X-data ; move Freescale Semiconductor 200,55,0,0,0 ; Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address P:START #$0d0000,x:M_PCTL ; PLL enable ; CLKOUT disable #INT_PROG,r0 ...
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... INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f, #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr x:0 $262EB9 $86F2FE $E56A5F DSP56366 Technical Data, Rev. 3.1 y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 Freescale Semiconductor ...
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... Freescale Semiconductor $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 ...
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... DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... YDAT_END Freescale Semiconductor $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 DSP56366 Technical Data, Rev. 3.1 A-5 ...
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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...