DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 100

IC DSP 24BIT AUD 120MHZ 144-LQFP

DSPB56366AG120

Manufacturer Part Number
DSPB56366AG120
Description
IC DSP 24BIT AUD 120MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet

Specifications of DSPB56366AG120

Interface
Host Interface, I²C, SAI, SPI
Clock Rate
120MHz
Non-volatile Memory
ROM (240 kB)
On-chip Ram
69kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 110°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5.4
The following explanations should be considered as general observations on expected PLL behavior.
There is no testing that verifies these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.
5.4.1
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL
and the internal DSP clock for a given device in specific temperature, voltage, input frequency and MF.
These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz
and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this jitter is less than ±2 ns.
5.4.2
The frequency jitter of the PLL is defined as the variation of the frequency of the internal DSP clock. For
small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is
between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.
5.4.3
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL
is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency
of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be
2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the
prescribed values.
5-4
PLL Performance Issues
I
I
F2
F1
typF2
typF1
Phase Jitter Performance
Frequency Jitter Performance
Input (EXTAL) Jitter Requirements
F1 should be significantly less than F2. For example, F2 could be 66 MHz
and F1 could be 33 MHz. The degree of difference between F1 and F2
determines the amount of precision with which the current rating can be
determined for an application.
= current at F2
= current at F1
= high frequency (any specified operating frequency)
= low frequency (any specified operating frequency lower than F2)
I MIPS
=
DSP56366 Technical Data, Rev. 3.1
I MHz
=
NOTE
I (
typF2
I
typF1
)
(
F2
=
F1
)
Freescale Semiconductor

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