DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 33

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
No.
14
15
16
17
18
19
20
21
24
25
26
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution
Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts
Delay from RD assertion to interrupt request deassertion for
level sensitive fast interrupts
Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts
Duration for IRQA assertion to recover from Stop state
Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is active during Stop (PCTL Bit 17 = 1) (implies no
delay is enabled (OMR Bit 6 = 0)
delay is not enabled (OMR Bit 6 = 1)
Stop Delay)
delay is enabled (OMR Bit 6 = 0)
delay is not enabled (OMR Bit 6 = 1)
Stop delay)
2, 7
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
5
2, 7
5
5
DSP56366 Technical Data, Rev. 3.1
PLC × ET
3.75 × T
3.25 × T
PLC × ET
PLC × ET
PLC × ET
(WS + 3.5) × T
(WS + 3.5) × T
(WS + 2.5) × T
(WS + 3) × T
(8.25 ± 0.5) × T
4.25 × T
7.25 × T
10 × T
PLC/2) × T
C
C
C
Expression
PLC/2) × T
C
C
0.5) × T
× PDF + (20.5 ± 0.5)
C
+ WS × T
+ WS × T
5.5 × T
× PDF + (128 K −
× PDF + (23.75 ±
× PDF + (128K −
× T
C
C
C
C
+ 5.0
C
+ 2.0
+ 2.0
C
C
C
C
C
– 10.94
– 10.94
– 10.94
– 10.94
C
1
C
C
C
(continued)
– 10.94
– 10.94
C
37.4
62.4
88.3
64.6
45.8
Min
0.0
5.5
5.5
4.9
—
—
—
—
—
—
—
—
—
—
Note 6
Note 6
Note 6
Note 6
Note 6
Note
Max
72.9
—
—
—
—
—
—
—
—
—
—
—
—
6
Unit
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-7