DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 102

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.2
5-6
•
•
sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then
polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together
with the INIT and then polling INIT, ISR, and the HOREQ pin).
Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF
status bits are set or cleared by the host processor side of the interface. These bits are individually
synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)
Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits
HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have
significance). A very small probability exists that the DSP will read the status bits synchronized
during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
DSP Programming Considerations
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor