EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 12

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 12
Phase-Locked Loop
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For more information about making remote system upgrade, refer to the
System Upgrade with Cyclone III Devices
Handbook.
For more information about the altremote_update megafunction, refer to the
altremote_update Megafunction User Guide.
Cyclone III PLLs have a number of advanced features available including clock
multiplication and division, phase shifting, programmable duty cycles, clock
switchover, PLL cascading, PLL dynamic reconfiguration, dynamic phase shifting,
spread-spectrum clocking, external clock outputs and control signals.
For more information about the PLL features, refer to the
Cyclone III Devices
Previously, PLLs in the Cyclone series devices’ FPGAs were designed to be configured
for a specific input frequency. The newly added voltage-controlled oscillator (VCO)
range detector in the Cyclone III PLLs, together with the dynamic phase
reconfiguration and PLL reconfiguration, enable the support for advanced display
applications where the PLL input frequency may not be known ahead of time or may
change.
For information about the VCO range detector and the reference design to support the
unknown F
with PLLs
PLL Applications
In general, you can use the PLLs for frequency synthesis and clock management. The
PLL usage helps to compensate the clock delay for large clock networks to improve
performance. You can also use the PLLs to recover clocks and clean jitter caused by
the transmission signal line. The programmability of the FPGA makes it easy to
change the parameters such as the frequency, bandwidth and duty cycle.
Before you start your design using a PLL, make sure you define the correct
applications for the PLL.
Define PLL Settings
Based on the features that are available in the Cyclone III device that you are
targeting, define the settings of the PLL based on the system requirement. The
following guidelines help you to decide on the settings.
PLL Input and Output Frequencies
Based on your system requirement, define the input frequencies and output
frequencies for the PLL. Cyclone III PLLs can operate in a particular bandwidth. If the
input frequencies and output frequencies do not meet that bandwidth, you can
cascade the PLLs. Cyclone III PLL clock inputs can only be fed by dedicated clock
input pins or outputs from another PLL. PLL clock inputs cannot be fed by internally
generated logic or clock source that originates from the general purpose I/O pins.
PLL clock outputs can drive the dedicated clock output pin or global clock networks.
white paper.
ref
video applications, refer to
chapter in volume 1 of the Cyclone III Device Handbook.
chapter in volume 1 of the Cyclone III Device
Supporting Unknown F
Clock Networks and PLLs in
© November 2008 Altera Corporation
REF
Video Applications
Early System Planning
Remote