EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 3

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Early System Planning
Table 2. Cyclone III FPGA Package Options and I/O Pin Counts
Speed Grade
Early System Planning
© November 2008 Altera Corporation
Notes to
(1) For more information about the device packaging specifications, refer to the support section of the Altera website.
(2) The numbers are the maximum I/O counts (including clock input pins) supported by the device-package combination and can be affected by the
(3) All the packages are available in lead-free and leaded options.
(4) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/O is restricted to 510 I/Os if you enable migration
(5) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground
(6) All the UBGA packages are supported by the Quartus II software version 7.1 SP1 and later, with the exception of the UBGA packages of EP3C16,
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
Device
(www.altera.com/support/devices/packaging/specifications/pkg-pin/spe-index.html).
configuration scheme selected for the device.
to the EP3C120 and are using voltage referenced I/O standards. If you are not using voltage referenced I/O standards, the maximum number of
I/Os can be increased.
plane on your PCB. This exposed pad is used for electrical connectivity and not for thermal purposes.
which is supported by the Quartus II software version 7.2.
Table
(EQFP)
Enhanced
Quad Flat
2:
144-pin
Plastic
Pack
94
94
84
82
—
—
—
—
(5)
Device speed grade affects the timing closure of the device. Depending on the density
and package, Cyclone III devices are available in three different speed grades:
■
■
■
When migrating to a device of different speed grade, check the timing report from the
timing analysis to ensure that there is no timing violation between different blocks
within the Cyclone III device, between the Cyclone III device and other devices on the
board. Always design with a sufficient timing margin so that your design can work on
devices of different speed grades. Generally, the difference of one speed grade can
mean a core f
It is important to know your system requirement and what your Cyclone III device
can offer at the early stage of the design cycle.
Ball-Grid
–6 (fastest),
–7 and,
–8
FineLine
164-pin
(MBGA)
Micro
Array
106
106
92
—
—
—
—
—
Quad Flat
MAX
240-pin
(PQFP)
Plastic
Pack
160
148
128
—
—
—
—
—
or I/O performance difference of up to 20%.
Ball-Grid
FineLine
256-pin
(FBGA)
Array
182
182
168
156
—
—
—
—
(UBGA)(6)
(Note
FineLine
Ball-Grid
256-pin
Array
Ultra
182
182
168
156
—
—
—
—
1), (2),
Ball-Grid
FineLine
(3)
324-pin
(FBGA)
Array
215
195
—
—
—
—
—
—
Ball-Grid
FineLine
484-pin
(FBGA)
Array
346
331
327
295
283
—
—
—
(UBGA)(6)
Ball-Grid
FineLine
484-pin
Array
Ultra
346
331
327
295
—
—
—
—
Ball-Grid
FineLine
780-pin
(FBGA)
535
Array
Page 3
377
429
531
—
—
—
—
(4)