EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 20

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 20
f
f
The V
1.8, 2.5, 3.0 and 3.3 V. Each bank can support a different voltage level. The V
serves as an input reference voltage for the voltage reference I/O standards and is
used mainly for a voltage bias and does not source or sink much current. The voltage
can be created with a regulator or a resistor divider network. If voltage reference I/O
standards are not used in the bank, the VREF pins are available as user I/O pins
In Cyclone III devices, Altera suggests that you use a linear regulator to power the
V
rails with the linear or switching regulators depending on the efficiency or cost
considerations.
To reduce system noise, it is important to ensure that the power supply is clean. Place
a ferrite bead and tantalum parallel capacitors where the power supply enters the
board’s power plane to filter out the noise to the power plane. Generally, the tantalum
capacitors are used for circuits which demand high stability in the capacitance values.
The ferrite bead should be connected in series between the power supply and the
power plane, while the capacitors are connected between the power plane and
ground, in parallel with each other. Decoupling depends on the design decoupling
requirements of the specific board.
For information on minimizing noise for power supplies, refer to
Board Layout Guidelines
Because the PLL contains analog components embedded in a digital device, there are
several considerations for designing the PLL power supply and minimizing jitter.
■
■
■
■
■
■
For more information about the decoupling strategy for Cyclone III power supplies,
refer to
CCA
To minimize jitter,
■
■
Make sure all VCCA and VCCD_PLL power pins are connected to a 2.5-V and 1.2-V
power supply respectively, regardless of whether you are using any PLL in the
device or not.
Use an isolated linear regulator to power the VCCA pin.
Connect the VCCD_PLL power pin to the quietest digital supply on the board.
Filter each VCCA and VCCD_PLL power pin with a decoupling circuit. Refer to
Cyclone III device pin-out for recommendation.
The GNDA pins should be connected to an isolated analog ground plane on the
board.
pins because they power the analog circuitry. You can power the digital voltage
CCIO
Run a thick trace (at least 20 mils) from the power supply to each VCCA pin.
Connect all VCCD_Pll power pins to the quietest digital supply on the board
Cyclone III Device Family Pin Connection Guidelines.
pin connections depend on the design’s I/O standards, and support 1.2, 1.5,
and
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
© November 2008 Altera Corporation
Board Design Considerations
AN 224: High-Speed
REF
pin