EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 45

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Verification
Verification
Timing Closure and Verification
© November 2008 Altera Corporation
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In addition, there is a limit for total current sink or source for a set of consecutive
output pads. As this relates to the location of pads, use the Quartus II software to
check for this violation by providing the pin’s maximum DC current. To set this in the
Quartus II software, go to the Assignment Editor and enter the maximum DC current
to Electromigration Current assignment for the pin. To view the DC restrictions in the
Quartus II software, on the Assignments menu, click Device. Click Device & Pin
Options and select the Pin Placement tab. The restrictions are listed in
Electromigration window.
For the specification on current limit, refer to the Pad Placement and DC Guidelines
section in the
Device Handbook.
This section provides information about verifying your design in the areas of timing,
power consumption, and simulation.
After compiling the completed logic design, check the device utilization and verify
that the design meets its timing requirements. Analyze the messages generated
during the compilation to check for any potential problems. If required, you can use
the Quartus II software to optimize the design's resource utilization and achieve
timing closure, preserve the performance of unchanged design blocks, and reduce
compilation time for future iterations. You can also verify the design functionality
with simulation. This section provides the guidelines for these stages of the
compilation flow.
Timing Constraints and Analysis
Timing constraints are critical to ensure that the designs meet their timing
requirements, as timing requirements represent actual design requirements that must
be met for the device to operate correctly.
The Quartus II software includes the Quartus II TimeQuest Timing Analyzer, a
powerful ASIC-style timing analysis tool that validates the timing performance of all
logic in your design. It supports the industry-standard Synopsys Design Constraints
(SDC) format timing constraints, and has an easy-to-use GUI with interactive timing
reports. It is ideal for constraining high-speed source-synchronous interfaces and
clock multiplexing design structures.
For legacy designs, the Quartus II software also includes the Classic Timing Analyzer,
which uses different design constraints and reports.
The software also supports static timing analysis in the industry-standard Synopsys
Primetime software. Specify the tool in the New Project Wizard or the EDA Tools
Settings page of the Settings dialog box to generate the required timing netlist.
Cyclone III Device I/O Features
chapter in volume 1 of the Cyclone III
Page 45