EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 23

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Board Design Considerations
Configuration Pin Connections
© November 2008 Altera Corporation
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1
Depending on your configuration scheme, different pull-up or pull-down resistor or
signal integrity requirements may apply. Some configuration pins also have specific
requirements if unused. It is important to correctly connect the configuration pins.
This section provides guidelines to address common issues.
The internal PCI clamping diode for the dual-purpose configuration pin is turned off
if the pin is part of the selected configuration scheme in your Quartus II project.
For a list of the dedicated and dual-purpose configuration pins, and a description of
the function and connection guidelines, refer to the
chapter in volume 1 of the Cyclone III Device Handbook.
Configuration and JTAG Pins I/O Voltage Requirements
When using a serial configuration device in the AS configuration scheme, you must
connect a 25-
DATA[0]. When cascading Cyclone III devices in multi-device configuration, you
must connect repeater buffers between the Cyclone III master and slave device for
DATA and DCLK. The output resistance of the repeater buffers has to fit the maximum
overshoot equation given by 0.8Z
transmission line impedance and R
For information about configuration requirements, refer to the
Devices
DCLK/TCK Signal Integrity
Adopt good design techniques to ensure that the DCLK and TCK traces on your board
produce clean signals with no overshoot, undershoot, or ringing. When designing the
board, lay out the DCLK and TCK traces using the same techniques used to lay out a
clock line. A noisy DCLK signal could affect configuration and cause an nSTATUS
error. Ensure that the TCK trace produces a clean signal with no overshoot,
undershoot, or ringing. For a chain of Cyclone III devices, noise on any of the DCLK or
TCK pins of each device in the chain could cause configuration or JTAG programming
to fail for the whole chain.
For more information about connecting devices in a chain, refer to the
Cyclone III Devices
JTAG/Configuration Pin Pull-up/Down
Noise at the JTAG pins, whether the device is in ISP or user mode, or during power
up, can cause the device to go into an undefined state or mode. Altera recommends
pulling the TCK pin low and the TMS pin high through resistors.
The JTAG circuitry is activated when V
are connected to V
floating. Any transition on the TCK pin can cause the JTAG state machine to transition
to an unknown state, leading to incorrect operation when V
To disable the JTAG state machine during power-up, the TCK pin should be pulled
low to ensure that an inadvertent rising edge does not occur on TCK.
chapter in volume 1 of the Cyclone III Device Handbook.
Ω
series resistor at the near end of the serial configuration device for the
chapter in volume 1 of the Cyclone III Device Handbook.
CCIO
and the V
CCIO
O
= R
E
is the equivalent resistance of the output buffer.
is not powered up, the JTAG signals are left
E
CCINT
= 1.8Z
is powered up. If the TMS and TCK pins
O
. In this equation, Z
Configuring Cyclone III Devices
CCIO
Configuring Cyclone III
is finally powered up.
O
is the
Configuring
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