EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 36

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 36
Design and Compilation
f
For more information about using the incremental compilation flows in the Quartus II
software, as well as important guidelines for creating design partitions and a design
floorplan, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based
Design
chapter in volume 1 of the Quartus II Handbook.
Design Partitions
When partitioning a design for an FPGA, register the partition of the I/O boundaries
to keep critical timing paths inside one partition that can be optimized independently.
When the design partitions are specified, you can use the Incremental Compilation
Advisor to ensure that the partitions meet Altera's recommendations.
Having the source code for each design block in a separate file allows you to make
changes to the block separately. If you use a third-party synthesis tool, create a
separate .vqm or .edf netlist for each design partition in your synthesis tool. Refer to
your synthesis tool documentation for information on the support for the Quartus II
incremental compilation. Use the hierarchy in your design to provide more flexibility
when partitioning. The top level of the hierarchy should have very little logic, and the
lower-level design blocks contain the most logic.
Timing Budget and Resource Allocation
In a team-based design, if you optimize the lower-level partitions separately, any
unregistered path that crosses between the partitions are not optimized as an entire
path when the partitions are integrated. For each unregistered timing path that
crosses between the partitions, make the timing assignments on the corresponding
I/O path in each partition to constrain both ends of the path to the budgeted timing
delay. The software optimizes the paths appropriately so the paths can meet the
top-level design requirements when the partitions are connected together in the
top-level design.
When performing incremental compilation, the software synthesizes each partition
separately with no data about the resources used in other partitions. Allocating
resource utilization among the design partitions for example logic, memory,
multipliers, PLLs and global routing signals avoids any problems with conflicting
resources when all the partitions are integrated.
Planning in Bottom-Up and Team-Based Flows
In bottom-up design flows, top-level project information, such as the pin locations,
physical constraints, and timing requirements, should be communicated to the
designers of the lower-level partitions before they start their design to avoid problems
during system integration.
The system architect can plan the design partitions at the top level and use the
Quartus II incremental compilation to communicate information to lower-level
designers through automatically-generated scripts. The Quartus II software’s
Generate bottom-up design partition scripts option automates the process of
transferring top-level project information to lower-level modules. The software
provides a project manager interface for managing project information in the top-level
design.
© November 2008 Altera Corporation