EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 47

IC CYCLONE III FPGA 55K 484 FBGA

EP3C55F484I7

Manufacturer Part Number
EP3C55F484I7
Description
IC CYCLONE III FPGA 55K 484 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484I7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Verification
Figure 8. Early Timing Estimate
© November 2008 Altera Corporation
f
f
Checking Design Timing
To ensure that your design works, check the timing report to ensure that there is no
timing violation. It is important that the internal and I/O timings are met. The f
from the timing report indicates the maximum frequency at which your design can
operate. To ensure that the Cyclone III device interfaces correctly with other devices
on the board, check the t
when the Cyclone III device receives data from another device, make sure that the t
and t
register. Violating t
Metastable output can become incorrect for short durations, thus affecting the design
functionality.
When the Cyclone III device transmits registered data to another device, check the t
of the Cyclone III device to estimate the data arrival time for the external device.
For more information about the TimeQuest Timing Analyzer and the Classic Timing
Analyzer, refer to the
Timing Analyzer
For more information about metastability, refer to
Devices.
H
are not violated when the data is being clocked into the Cyclone III device
chapters, respectively, in volume 3 of the Quartus II Handbook.
SU
or t
Quartus II TimeQuest Timing Analyzer
SU
H
, t
can cause the register output to become metastable.
CO
, t
H
, and t
PD
values from the timing report. For example,
AN 42: Metastability in Altera
and the
Quartus II Classic
MAX
Page 47
CO
SU

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