EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 37

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Design and Compilation
Power Optimization
© November 2008 Altera Corporation
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Creating a Design Floorplan
Create a design floorplan to avoid resource and location conflicts between the design
partitions. Floorplan assignments are recommended for timing-critical partitions in
top-down flows. You can use the Quartus II Chip Planner to create a design floorplan
using LogicLock region assignments for each design partition. The floorplan editor
enables you to view connections between regions, estimate physical timing delays on
the chip, and move regions around the device floorplan. When you have compiled the
full design, you can also view logic placement and locate areas of routing congestion
to improve the floorplan assignments.
For more information about creating placement assignments in the design floorplan,
refer to the
Quartus II Handbook.
This section describes the various Quartus II software features and design techniques
that help to reduce your design power consumption.
Quartus II Power Optimization Features
The Quartus II software offers power-driven compilation to reduce your design core
dynamic power. Depending on the design, power-optimized synthesis and fitting can
help reduce dynamic power by an average of up to 16%. Altera recommends
activating both the options to achieve minimal power consumption. However, you
should prioritize your design timing constraint requirements over power
optimization.
The Quartus II software includes the Power Optimization Advisor to provide
recommendations to reduce power based on the current design project settings and
assignments. Each recommendation includes a description, a summary of the effect
and the actions required to make the appropriate settings. The recommendations are
split into stages to show the order in which you should apply the settings. After
making any of the recommended changes, recompile your design and run the
PowerPlay Power Analyzer to check the change in your power results.
For more information on power-driven compilation and Power Optimization
Advisor, refer to the
Handbook and the Quartus II Help.
The Design Space Explorer (DSE) is an utility in the Quartus II software that can be
used to find the optimal Quartus II software settings to minimize your design power
consumption.
For more information on the DSE, refer to the
volume 2 of the Quartus II Handbook.
Design Power Optimization Techniques
This section provides guidelines on design techniques that affect overall design
power. The results of these techniques may be different from design to design.
Analyzing and Optimizing the Design Floorplan
Power Optimization
chapter in volume 2 of the Quartus II
Design Space Explorer
chapter in volume 2 of the
chapter in
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