EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 7

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Early System Planning
© November 2008 Altera Corporation
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Cyclone III devices offer configuration data decompression and real-time remote
system upgrades to save configuration memory space and time. Support for these
configuration features varies depending on your configuration scheme. Cyclone III
devices also include optional configuration pins and a reconfiguration option that you
must determine at the start and set up in the Quartus II software, so that you have all
the information required for your board and system design. For the Quartus II
software settings and pins related to the configuration options that affect your board
and system design, refer to
Depending on the device densities and package options, you can configure
Cyclone III devices using one of the following five configuration schemes:
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■
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A selection of configuration scheme with different configuration voltage standards is
selected by driving the Cyclone III device’s MSEL pins either high or low. Depending
on the MSEL pin settings, you can either select a fast power-on reset (POR) time or a
standard POR time. The fast POR time supports fast wake-up time applications,
where it may be necessary for a device to wake up quickly to begin operation.
In Cyclone III devices, the supported configuration schemes differ for different device
densities and package options. For example, the EP3C16 device’s E144 package offers
the AS, PS, and JTAG schemes while its U484 package offers the AS, PS, FPP, AP, and
JTAG schemes.
For more information about the supported configuration schemes, refer to the
Cyclone III devices’
For complete information about the Cyclone III supported configuration schemes
across device densities and package options, configuration voltage standards and
POR time, ways to execute the required configuration schemes and all the necessary
option pin settings, including the MSEL pin settings, refer to the
Devices
For the new user of Altera device configuration schemes, the available choice of
configuration schemes and methods in which the configuration schemes can be set up
may be overwhelming. In general, Altera configuration schemes are categorized into
the following configuration schemes:
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■
Active serial (AS)
Active parallel (AP)
Passive serial (PS)
Fast passive parallel (FPP)
Joint Test Action Group (JTAG)
Active configuration scheme
Passive configuration scheme
chapter in volume 1 of the Cyclone III Device Handbook.
Configuration
“Design and
Center.
Compilation”.
Configuring Cyclone III
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