EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 110
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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PLLs and Clock Networks
Figure 2–72. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL
Outputs
Notes to
(1)
(2)
2–102
Stratix II GX Device Handbook, Volume 1
Clock pins
CLK0p
CLK1p
CLK2p
CLK3p
Left Side Global and Regional
Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
Clock Network Connectivity
(Part 1 of 3)
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
EP2SGX30C/D and EP2SGX60C/D devices only have two fast PLLs (1 and 2); they do not contain corner fast
PLLs.
Notes
Figure
(1),
2–72:
(2)
PLL 7
PLL 8
Fast
Fast
C0
C1
C2
C3
C0
C1
C2
C3
v
v
RCLK0
RCLK4
v
v
RCLK1
RCLK5
v
v
RCLK2
RCLK6
v
v
RCLK3
RCLK7
v
GCLK0
v
GCLK1
v
GCLK2
v
GCLK3
v
Altera Corporation
v
October 2007
v
v
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