EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 127

• Manufacturer Part Number: EP2SGX30CF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30CF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1750

Figure 2–82. Stratix II GX IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
DQS Local
2–82:
Bus (2)
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
Input Register
Input Register
D
CLRN/PRN
ENA
D
CLRN/PRN
ENA
Input RegisterDelay
I
nput Pin to
Q
Q
Note (1)
Stratix II GX Device Handbook, Volume 1
D
ENA
CLRN/PRN
To DQS Logic
Latch
Block (3)
Q
VCCIO
Stratix II GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–119