EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 154
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Document Revision History
2–146
Stratix II GX Device Handbook, Volume 1
Table 2–42. Document Revision History (Part 4 of 6)
Document
Date and
Version
Updated:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Updated bulleted lists at the beginning of the
“Transceivers” section.
Added reference to the “Transmit Buffer”
section.
Deleted the Programmable V
“Programmable Output Driver” section.
Data Width” heading in Table 2–14.
Deleted “Global & Regional Clock
Connections from Right Side Clock Pins &
Fast PLL Outputs” table.
Updated notes to Tables 2–29 and 2–37.
Updated notes to Figures 2–72, 2–73 and
2–74.
Updated bulleted list in the “Advanced I/O
Standard Support” section.
Changed “PLD Interface” heading to “Parallel
“Transmitter PLLs”
“Transmitter Phase Compensation FIFO
Buffer”
“8B/10B Encoder”
“Byte Serializer”
“Programmable Output Driver”
“Receiver PLL & CRU”
“Programmable Pre-Emphasis”
“Receiver Input Buffer”
“Control and Status Signals”
“Programmable Run Length Violation”
“Channel Aligner”
“Basic Mode”
“Byte Ordering Block”
“Receiver Phase Compensation FIFO
Buffer”
“Loopback Modes”
“Serial Loopback”
“Parallel Loopback”
“Regional Clock Network”
“MultiVolt I/O Interface”
“High-Speed Differential I/O with DPA
Support”
Changes Made
OD
table from the
Summary of Changes
Altera Corporation
October 2007
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