EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 217
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
June 2009
Note to
(1)
V
V
V
V
V
R
V
V
V
V
V
R
Table 4–29. 2.5-V LVDS I/O Specifications
Table 4–30. 3.3-V LVDS I/O Specifications
Symbol
Symbol
CCIO
ID
ICM
OD
OCM
CCIO
ID
ICM
OD
OCM
L
L
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
(1)
Table
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
I/O supply voltage for top and
bottom PLL banks (9, 10, 11,
and 12)
Input differential voltage
swing (single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode
voltage
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
4–30:
Parameter
Parameter
R
R
R
R
L
L
L
L
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
Conditions
Conditions
Minimum
Minimum
2.375
1.125
3.135
100
200
250
100
200
250
840
Stratix II GX Device Handbook, Volume 1
90
90
DC and Switching Characteristics
Typical
Typical
1,250
1,250
350
100
350
100
2.5
3.3
Maximum
Maximum
CCINT
2.625
1,800
1.375
3.465
1,800
1,570
900
450
110
900
710
110
, not V
CCIO
Unit
Unit
4–47
mV
mV
mV
mV
mV
mV
mV
V
V
Ω
V
Ω
.
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