EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 113
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–73. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs
Notes to
(1)
(2)
Altera Corporation
October 2007
EP2SGX30C/D and EP2SGX60C/D devices only have two enhanced PLLs (5 and 6), but the connectivity from these
two PLLs to the global and regional clock networks remains the same as shown.
If the design uses the feedback input, you will lose one (or two, if FBIN is differential) external clock output pin.
Notes
Figure
(1),
2–73:
(2)
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
Figure 2–73
outputs and top and bottom CLK pins.
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
(2)
shows the global and regional clocking from enhanced PLL
(2)
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 6
PLL 5
(2)
(2)
Stratix II GX Device Handbook, Volume 1
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Stratix II GX Architecture
2–105
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