EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 13
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–3. Clock Distribution for the Transmitters
Note to
(1)
Altera Corporation
October 2007
Reference Clocks
(refclks,
Global Clock (1) ,
Inter-Transceiver
Lines)
The global clock line must be driven by an input pin.
Figure
2–3:
Central Block
Transmitter Channel [3..2]
Transmitter Channel [1..0]
Transmitter PLL Block
The transmitter PLLs in each transceiver block clock the PMA and PCS
circuitry in the transmit path. The Quartus II software automatically
powers down the transmitter PLLs that are not used in the design.
Figure 2–4
The transmitter phase/frequency detector references the clock from one
of the following sources:
■
■
■
■
Two reference clocks, REFCLK0 and REFCLK1, are available per
transceiver block. The inter-transceiver block bus allows multiple
transceivers to use the same reference clocks. Each transceiver block has
one outgoing reference clock which connects to one inter-transceiver
block line. The incoming reference clock can be selected from five
inter-transceiver block lines IQ[4..0] or from the global clock line that
is driven by an input pin.
Reference clocks
Reference clock from the adjacent transceiver block
Inter-transceiver block clock lines
Global clock line driven by input pin
is a block diagram of the transmitter PLL.
Note (1)
Transmitter Local
Clock Divider Block
Transmitter Local
Clock Divider Block
Central Clock
Gen Block
Divider Block
Gen Block
TX Clock
TX Clock
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Transmitter High-Speed &
Transmitter High-Speed &
Low-Speed Clocks
Low-Speed Clocks
2–5
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