EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 226

IC STRATIX II GX 30K 780-FBGA

EP2SGX30CF780C5N

Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30CF780C5N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2SGX30CF780C5N
0
Operating Conditions
4–56
Stratix II GX Device Handbook, Volume 1
Low
sustaining
current
High
sustaining
current
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
25-Ω R
3.3/2.5
50-Ω R
3.3/2.5
Parameter
Table 4–48. Bus Hold Parameters
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 1 of 2)
Symbol
S
S
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
V
(maximum)
V
(minimum)
0 V < V
V
0 V < V
V
Conditions
IN
IN
CCIO
CCIO
> V
< V
IL
IH
IN
IN
Description
<
<
–22.5
Bus Hold Specifications
Table 4–48
On-Chip Termination Specifications
Tables 4–49
resistance tolerance when using series or differential on-chip termination.
22.5
0.45
Min
1.2 V
–120
Max
0.95
120
shows the Stratix II GX device family bus hold specifications.
and
Min
–25
0.5
25
V
V
V
V
4–50
1.5 V
CCIO
CCIO
CCIO
CCIO
–160
Max
160
1.0
Conditions
define the specification for internal termination
= 3.3/2.5 V
= 3.3/2.5 V
= 3.3/2.5 V
= 3.3/2.5 V
0.68
Min
–30
V
30
CCIO
1.8 V
Level
–200
Max
1.07
200
Commercial
Max
Min
–50
±30
±30
0.7
±5
±5
50
2.5 V
Resistance Tolerance
–300
Max
300
1.7
Industrial
Altera Corporation
Max
± 30
Min
–70
±10
±30
0.8
±10
70
3.3 V
Notes
–500
Max
500
2.0
June 2009
(1),
Unit
%
%
%
%
Unit
μA
μA
μA
μA
(2)
V

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