EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 141
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
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On-Chip Parallel Termination with Calibration
Stratix II GX devices support on-chip parallel termination with
calibration for column I/O pins only. There is one calibration circuit for
the top I/O banks and one circuit for the bottom I/O banks. Each on-chip
parallel termination calibration circuit compares the total impedance of
each I/O buffer to the external 50-Ω resistors connected to the RUP and
RDN pins and dynamically enables or disables the transistors until they
match. Calibration occurs at the end of device configuration. Once the
calibration circuit finds the correct impedance, it powers down and stops
changing the characteristics of the drivers.
1
For more information about on-chip termination supported by Stratix II
devices, refer to the
Devices
For more information about tolerance specifications for on-chip
termination with calibration, refer to the
chapter in volume 1 of the Stratix II GX Device Handbook.
MultiVolt I/O Interface
The Stratix II GX architecture supports the MultiVolt I/O interface feature
that allows Stratix II GX devices in all packages to interface with systems
of different supply voltages. The Stratix II GX VCCINT pins must always
be connected to a 1.2-V power supply. With a 1.2-V V
pins are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The VCCIO pins can be
connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply,
depending on the output requirements. The output levels are compatible
with systems of the same voltage as the power supply (for example, when
VCCIO pins are connected to a 1.5-V power supply, the output levels are
compatible with 1.5-V systems). The Stratix II GX VCCPD power pins
must be connected to a 3.3-V power supply. These power pins are used to
supply the pre-driver power to the output buffers, which increases the
performance of the output pins. The VCCPD pins also power
configuration input pins and JTAG input pins.
chapter in volume 2 of the Stratix II GX Device Handbook.
On-chip parallel termination with calibration is only supported
for input pins.
Selectable I/O Standards in Stratix II & Stratix II GX
Stratix II GX Device Handbook, Volume 1
DC & Switching Characteristics
Stratix II GX Architecture
CCINT
level, input
2–133
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