EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 191

IC STRATIX II GX 30K 780-FBGA

EP2SGX30CF780C5N

Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30CF780C5N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2SGX30CF780C5N
0
Altera Corporation
June 2009
Sinusoidal jitter
FC-1
Deterministic jitter
FC-2
Random jitter FC-
2
Sinusoidal jitter
FC-2
Deterministic jitter
FC-4
Random jitter FC-
4
Sinusoidal jitter
FC-4
XAUI Transmit Jitter Generation
Total jitter at
3.125 Gbps
Deterministic jitter
at 3.125 Gbps
XAUI Receiver Jitter Tolerance
Total jitter
Deterministic jitter Pattern = CJPAT
Table 4–19. Stratix II GX Transceiver Block AC Specification
Description
Symbol/
Fc/25000
Fc/1667
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
Fc/25000
Fc/1667
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
Fc/25000
Fc/1667
REFCLK
156.25 MHz
Pattern = CJPAT
V
No Pre-emphasis
REFCLK
156.25 MHz
Pattern = CJPAT
V
No Pre-emphasis
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
No Equalization
DC Gain = 3 dB
OD
OD
= 1200 mV
= 1200 mV
Conditions
=
=
(9)
(9)
Commercial Speed
Min
-
-
-3 Speed
> 0.33
> 0.29
> 0.33
> 0.29
> 0.65
> 0.37
Grade
> 1.5
> 0.1
> 1.5
> 0.1
> 1.5
> 0.1
Typ
-
-
Max
0.17
0.3
Notes
Min
Commercial and
Industrial Speed
-
-
Stratix II GX Device Handbook, Volume 1
(1), (2),
-4 Speed
> 0.33
> 0.29
> 0.33
> 0.29
> 0.65
> 0.37
Grade
Typ
> 1.5
> 0.1
> 1.5
> 0.1
> 1.5
> 0.1
-
-
DC and Switching Characteristics
(3)
Max
0.17
0.3
(Part 4 of 19)
Commercial Speed
Min
-
-
-5 Speed
Grade
> 0.33
> 0.29
> 0.33
> 0.29
> 0.65
> 0.37
Typ
> 1.5
> 0.1
> 1.5
> 0.1
> 1.5
> 0.1
-
-
Max
0.17
0.3
4–21
Unit
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI

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