EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 228
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 228 of 316
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Operating Conditions
4–58
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
25-Ω R
3.3/2.5
50-Ω R
3.3/2.5/1.8
50-Ω R
R
C
C
C
C
C
C
Table 4–50. Series and Differential On-Chip Termination Specification for Left I/O Banks
Table 4–51. Stratix II GX Device Capacitance
D
IOTB
IOL
CLKTB
CLKL
CLKL+
OUTFB
Symbol
Symbol
On-chip parallel termination with calibration is only supported for input pins.
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
S
S
S
Table
Table
1.5
4–50:
4–51:
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
differential receiver and transmitter pins.
Input capacitance on top/bottom clock input pins:
CLK[12..15]
Input capacitance on left clock inputs:
Input capacitance on left clock inputs:
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 11 and 12.
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal differential termination for
LVDS (100-Ω setting)
Description
Pin Capacitance
Table 4–51
.
shows the Stratix II GX device family pin capacitance.
Parameter
Note (1)
CLK0
CLK1
V
V
V
V
CCIO
CCIO
CCIO
CCIO
Conditions
= 3.3/2.5V
= 3.3/2.5/1.8V
= 1.5V
= 2.5 V
and
and
CLK2
CLK3
CLK[4..7]
.
.
and
Commercial
Max
±30
±30
±36
±20
Resistance Tolerance
Altera Corporation
Industrial
Typical
Note (1)
5.0
6.1
6.0
6.1
3.3
6.7
Max
±30
±30
±36
±25
June 2009
Unit
Unit
pF
pF
pF
pF
pF
pF
%
%
%
%
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