EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 71
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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MultiTrack
Interconnect
Altera Corporation
October 2007
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear and load/preset
signals. The ALM directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT
gate push-back technique. Stratix II GX devices support simultaneous
asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one load/preset signal.
In addition to the clear and load/preset ports, Stratix II GX devices
provide a device-wide reset pin (DEV_CLRn) that resets all registers in the
device. An option set before compilation in the Quartus II software
controls this pin. This device-wide reset overrides all other control
signals.
In the Stratix II GX architecture, the MultiTrack interconnect structure
with DirectDrive technology provides connections between ALMs,
TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
re-optimization cycles that typically follow design changes and
additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory in the same row.
These row resources include:
■
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the
device
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–63
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