EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 130

• Manufacturer Part Number: EP2SGX30CF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30CF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1750

I/O Structure
Figure 2–85. Output Timing Diagram in DDR Mode
2–122
Stratix II GX Device Handbook, Volume 1
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130 1,508-pin FineLine BGA
Table 2–31. DQS and DQ Bus Mode Support
Device
From Internal
Registers
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
DDR output
CLK
Package
The Stratix II GX IOE operates in bidirectional DDR mode by combining
the DDR input and DDR output configurations. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II GX devices also
have dedicated phase-shift circuitry for interfacing with external memory
interfaces, including DDR and DDR2 SDRAM, QDR II SRAM,
RLDRAM II, and SDR SDRAM. In every Stratix II GX device, the I/O
banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device
support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18,
or ×32/×36.
supported per device.
A1
B1
B1
A1
Table 2–31
B2
A2
B2
Number of
×4 Groups
A2
18
18
36
36
36
36
shows the number of DQ and DQS buses that are
A3
B3
B3
A3
×8/×9 Groups
Number of
A4
B4
B4
18
18
18
18
8
8
A4
Number of
×16/×18
Groups
4
4
8
8
8
8
Altera Corporation
October 2007
Number of
×32/×36
Groups
0
0
4
4
4
4