CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet
CY8CTMG201-48LTXI
Specifications of CY8CTMG201-48LTXI
Related parts for CY8CTMG201-48LTXI
CY8CTMG201-48LTXI Summary of contents
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PSoC CY8CTMG20x, CY8CTMG20xA, CY8CTST200, CY8CTST200A TRM ® PSoC CY8CTMG20x, CY8CTMG20xA, Technical Reference Manual (TRM) CY8CTST200, CY8CTST200A Document No. 001-53603 Rev. *C Phone (USA): 800.858.1810 Phone (Intnl.): 408.943.2600 December 11, 2009 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 [+] ...
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... C Patent Rights to use these components Specification as defined by Philips. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create ...
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Contents Overview Section A: Overview 1. Pin Information .......................................................................................................................... 19 Section B: PSoC Core 2. CPU Core (M8C) ........................................................................................................................ 27 3. Supervisory ROM (SROM) ......................................................................................................... 33 4. RAM Paging ............................................................................................................................... 39 5. Interrupt Controller ..................................................................................................................... 45 6. General Purpose I/O ...
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Contents Overview 4 [+] Feedback ...
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... CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout 20 1.1.3 CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32- Pin Part Pinout21 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC 48-Pin Part Pinout22 Section B: PSoC Core 2. CPU Core (M8C) 2.1 Overview.................................................................................................................................27 2.2 Internal Registers....................................................................................................................27 2 ...
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Contents 3.1.2.11 WriteAndVerify Function.............................................................................. 37 3.1.2.12 HWBootReset Function............................................................................... 38 3.2 Register Definitions ................................................................................................................ 38 4. RAM Paging 4.1 Architectural Description......................................................................................................... 39 4.1.1 Basic Paging..............................................................................................................39 4.1.2 Stack Operations ....................................................................................................... 40 4.1.3 Interrupts ................................................................................................................... 40 4.1.4 MVI Instructions......................................................................................................... 40 4.1.5 Current Page ...
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Internal Main Oscillator (IMO) 7.1 Architectural Description.........................................................................................................63 7.2 Application Overview ..............................................................................................................63 7.2.1 Trimming the IMO ......................................................................................................63 7.2.2 Engaging Slow IMO ...................................................................................................63 7.3 Register Definitions.................................................................................................................64 7.3.1 IMO_TR Register .......................................................................................................64 7.3.2 IMO_TR1 Register ....................................................................................................64 7.3.3 CPU_SCR1 Register .................................................................................................65 7.3.4 OSC_CR2 Register ...
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Contents 11.1.1.5 Sigma Delta................................................................................................. 89 11.1.2 IDAC .......................................................................................................................... 90 11.1.3 TrueTouch Counter ................................................................................................... 90 11.1.3.1 Operation .................................................................................................... 91 11.2 Register Definitions ............................................................................................................... 92 11.2.1 CS_CR0 Register ..................................................................................................... 92 11.2.2 CS_CR1 Register ..................................................................................................... 93 11.2.3 CS_CR2 Register ..................................................................................................... 93 11.2.4 CS_CR3 ...
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Register Definitions...............................................................................................................122 15.3.1 I2C_XCFG Register .................................................................................................122 15.3.2 I2C_XSTAT Register................................................................................................123 15.3.3 I2C_ADDR Register.................................................................................................123 15.3.4 I2C_BP Register ......................................................................................................123 15.3.5 I2C_CP Register ......................................................................................................124 15.3.6 CPU_BP Register ....................................................................................................124 15.3.7 CPU_CP Register....................................................................................................124 15.3.8 I2C_BUF Register....................................................................................................125 15.3.9 I2C_CFG Register ..................................................................................................126 15.3.10 I2C_SCR Register ..................................................................................................128 15.3.11 ...
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Contents 18.2 Register Definitions ..............................................................................................................147 18.2.1 SPI_TXR Register ...................................................................................................147 18.2.2 SPI_RXR Register...................................................................................................148 18.2.2.1 SPI Master Data Register Definitions........................................................148 18.2.2.2 SPI Slave Data Register Definitions..........................................................148 18.2.3 SPI_CR Register .....................................................................................................149 18.2.3.1 SPI Control Register Definitions................................................................149 18.2.4 SPI_CFG Register...................................................................................................150 18.2.4.1 SPI Configuration Register ...
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IMO_TR1 Register...................................................................................................181 20.3.16 Related Registers ....................................................................................................181 Section E: Registers 21. Register Reference 21.1 Maneuvering Around the Registers ......................................................................................187 21.2 Register Conventions ...........................................................................................................187 21.3 Bank 0 Registers ..................................................................................................................188 21.3.1 PRTxDR ..................................................................................................................188 21.3.2 PRTxIE ...................................................................................................................189 21.3.3 SPI_TXR .................................................................................................................190 21.3.4 SPI_RXR ................................................................................................................191 ...
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Contents 21.3.46 CUR_PP .................................................................................................................234 21.3.47 STK_PP ..................................................................................................................235 21.3.48 IDX_PP ...................................................................................................................236 21.3.49 MVR_PP .................................................................................................................237 21.3.50 MVW_PP ................................................................................................................238 21.3.51 I2C_CFG ................................................................................................................239 21.3.52 I2C_SCR ................................................................................................................240 21.3.53 I2C_DR ...................................................................................................................241 21.3.54 INT_CLR0 ...............................................................................................................242 21.3.55 INT_CLR1 ...............................................................................................................244 21.3.56 INT_CLR2 ...............................................................................................................246 21.3.57 INT_MSK2 ..............................................................................................................248 21.3.58 INT_MSK1 ..............................................................................................................249 ...
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Section A: Overview ® The PSoC family consists of many Programmable System-on-Chip with On-Chip Controller devices. The CY8CTMG20x and CY8CTST200 PSoC devices have fixed analog and digital resources in addition to a fast CPU, Flash program memory, and SRAM data ...
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Section A: Overview Top Level Architecture The PSoC block diagram on the next page illustrates the top-level architecture of the CY8CTMG20x CY8CTST200 devices. Each major grouping in the diagram is covered in this manual in its own section: PSoC Core, ...
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CORE SYSTEM BUS 1K, 2K Supervisory ROM (SROM) SRAM Interrupt Controller 6/12/24 MHz Internal Main Oscillator (IMO) SYSTEM BUS I2C USB Slave PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PSoC Core Top-Level Block Diagram Port 4 Port ...
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Section A: Overview Getting Started The quickest path to understanding PSoC is by reading the PSoC device’s data sheet and using PSoC Designer™ Integrated Development Environment (IDE). This manual is useful for understanding the details of the PSoC integrated circuit. ...
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Documentation Conventions There are only four distinguishing font types used in this manual, besides those found in the headings. The first is the use of italics when referencing a docu- ■ ment title or file name. The second is the ...
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Section A: Overview Acronyms This table lists the acronyms that are used in this manual. Acronyms Acronym Description ABUS analog output bus AC alternating current ADC analog-to-digital converter API Application Programming Interface BC broadcast clock BR bit rate BRA bus ...
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Pin Information This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8CTMG20x, CY8CTMG20xA, CY8CTST200, and CY8CTST200A PSoC devices. For up-to-date ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet or go ...
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Pin Information 1.1.2 CY8CTMG200-24LQXI, CY8CTMG200A-24LQXI, CY8CTST200-24LQXI, CY8CTST200A-24LQXI PSoC 24-Pin Part Pinout Table 1-2. 24-Pin QFN Part Pinout ** Type Pin Name No. Digital Analog P2[5] XTAL Out P2[3] XTAL P2[1] ...
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... CY8CTMG200-32LQXI, CY8CTMG200A-32LQXI, CY8CTST200-32LQXI, CY8CTST200A-32LQXI, CY8CTMG201-32LQXI, CY8CTMG201A-32LQXI PSoC 32-Pin Part Pinout Table 1-3. 32-Pin QFN Part Pinout ** Pin Name Description No. 1 IOH I P0[1] Integrating input P2[ P2[5] XTAL Out P2[3] XTAL P2[ P3[ P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO ...
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... Pin Information 1.1.4 CY8CTMG200-48LTXI, CY8CTMG200A-48LTXI, CY8CTST200-48LTXI, CY8CTST200A-48LTXI, CY8CTMG201-48LTXI, CY8CTMG201A-48LTXI PSoC 48-Pin Part Pinout Table 1-4. 48-Pin Part Pinout ** Pin Name Description No connection P2[ P2[5] XTAL Out P2[3] XTAL P2[ P4[ P4[ P3[ P3[ P3[ P3[1] 12 IOHR I P1[7] I2C SCL, SPI SS 13 IOHR I P1[5] I2C SDA, SPI MISO ...
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Section B: PSoC Core The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8CTMG20x or CY8CTST200 and the registers associated with those components. The core section covers the heart of the ...
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Section B: PSoC Core Core Register Summary This table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The grayed out bits are reserved bits. If you write these bits always write ...
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Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 1,DCh IO_CFG1 StrongP INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 64) 1,E8h IMO_TR 1,FAh IMO_TR1 x,FEh CPU_SCR1 IRESS 1,E2h OSC_CR2 INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 68) ...
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Section B: PSoC Core 26 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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CPU Core (M8C) This chapter explains the CPU Core, called the M8C, and its associated register. It covers the internal M8C registers, address spaces, instruction set and formats. For additional information concerning the M8C instruction set, refer to the ...
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CPU Core (M8C) 2.4 Instruction Set Summary The instruction set is summarized in both as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide ...
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Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags ADC A, expr ADC A, [expr ADC A, [X+expr ADC ...
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CPU Core (M8C) 2.5 Instruction Formats The M8C has a total of seven instruction formats that use instruction lengths of one, two, and three bytes. All instruc- tion bytes are taken from the program memory (Flash), using an address and ...
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Three-Byte Instructions The three-byte instruction formats are the second most prevalent instruction formats. These instructions need three bytes because they either move data between two addresses in the user accessible address space (registers and RAM) or they hold 16-bit ...
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CPU Core (M8C) 2.6 Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table show- ing the bit structure. The bits that are grayed out in the table are reserved ...
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Supervisory ROM (SROM) This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 3.1 Architectural Description The SROM holds code that boots ...
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Supervisory ROM (SROM) The following code example puts the correct value in KEY1 and KEY2. The code is preceded by a HALT, to force the program to jump directly into the setup code and not acci- dentally run into it. ...
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The IRAMDIS bit allows the preservation of variables even if a watchdog reset (WDR) occurs. The IRAMDIS bit is reset by all system resets except watchdog reset. Therefore, this bit is only useful for watchdog resets and not general resets. ...
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Supervisory ROM (SROM) An MVI A, [expr] instruction is used to move data from SRAM into Flash. Therefore, use the MVI read pointer (MVR_PP register) to specify which SRAM page from which data is pulled. Using the MVI read pointer ...
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Table 3-14. Flash Tables with Assigned Values Table 0 Silicon ID Low Byte Reserved Silicon ID High Byte Expected Numbers = Table 0 Reserved # Bits Used to Encode = Max Values (including 0) = Bits Targeted = IMO 6 ...
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Supervisory ROM (SROM) about 1 ms longer than WriteBlock (but still within the Twrite spec). The function performs a three-step process. In the first step, 128 bytes of data are moved from SRAM to the Flash. In the second step, ...
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RAM Paging This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM paging registers, refer to the Summary Table of the Core Registers on page address order, refer ...
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RAM Paging 4.1.2 Stack Operations As mentioned previously, the paging architecture's reset state puts the in a mode identical to that of a 256-byte device. Therefore, upon reset, all memory accesses are to Page 0. The SRAM page that stack ...
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ISR, the ISR is also required to restore the value before exe- cuting the RETI instruction. When the upper bit of the PgMode bits is set to ‘1‘, all nor- mal memory access is forced to the SRAM page indicated ...
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RAM Paging 4.2 Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that ...
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STK_PP Register Address Name Bit 7 Bit 6 0,D1h STK_PP The Stack Page Pointer Register (STK_PP) is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. Bits Page ...
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RAM Paging 4.2.6 MVW_PP Register Address Name Bit 7 Bit 6 0,D5h MVW_PP The MVI Write Page Pointer Register (MVW_PP) sets the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. Bits ...
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Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a hardware resource in PSoC devices to change program execution to a new address without regard to the current task ...
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Interrupt Controller 4. Program execution vectors to the interrupt table. Typi- cally an LJMP instruction in the interrupt table sends exe- cution to the user's interrupt service routine for this interrupt. (See Instruction Set Summary on page 5. The ISR ...
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The following table lists the interrupts and priorities that are available in the PSoC devices. Table 5-1. Device Interrupts Interrupt Interrupt Priority Address 0 (Highest) 0000h Reset 1 0004h Supply voltage monitor 2 0008h Analog 3 000Ch TrueTouch 4 0010h ...
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Interrupt Controller 5.3 Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables ...
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INT_CLR1 Register Address Name Bit 7 Bit 6 0,DBh INT_CLR1 Endpoint3 Endpoint2 This register enables the individual interrupt sources' ability to clear posted interrupts. When bits in this register are read, a '1' is returned for every bit position ...
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Interrupt Controller 5.3.3 INT_CLR2 Register Address Name Bit 7 Bit 6 0,DCh INT_CLR2 This register enables the individual interrupt sources' ability to clear posted interrupts. When bits in this register are read, a '1' is returned for every bit position ...
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INT_MSK0 Register Address Name Bit 7 Bit 6 0,E0h INT_MSK0 I2C Sleep The Interrupt Mask Register (INT_MSK0) enables the indi- vidual interrupt sources’ ability to create pending interrupts. If cleared, each bit in an INT_MSK0 register prevents a posted ...
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Interrupt Controller 5.3.6 INT_MSK2 Register Address Name Bit 7 Bit 6 0,DEh INT_MSK2 This register is used to enable the individual sources' ability to create pending interrupts. When an interrupt is masked off, the mask bit is '0'. The interrupt ...
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For additional information, refer to the page 252. 5.3.9 Related Registers CPU_F on page 254. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document ...
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Interrupt Controller 54 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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General Purpose I/O (GPIO) This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter- facing to the I/O pins of a PSoC device. The GPIO blocks provide the interface between ...
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General Purpose I/O (GPIO) 6.1.1 General Description The GPIO contains input buffers, output drivers, and config- uration logic for connecting the PSoC device to the outside world. IO Ports are arranged with (up to) 8 bits per port. Each full ...
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Vdd should be greater than 2.5V. 6.1.5 Port 0 Distinctions Port 0 has a stronger high drive. However, unlike Port 1, it does not have an option for regulating the ...
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General Purpose I/O (GPIO) Interrupt High mode. If the last value read from the GPIO was ‘1’, the GPIO is in Interrupt Low mode. Table 6-1. GPIO Interrupt Modes IE IOINT Description 0 0 Bit interrupt disabled, INTO deasserted 0 ...
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Register Definitions The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables ...
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General Purpose I/O (GPIO) 6.2.3 PRTxDMx Registers Address Name Bit 7 Bit 6 1,xxh PRTxDM0 1,xxh PRTxDM1 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded ...
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IO_CFG1 Register Address Name Bit 7 Bit 6 1,DCh IO_CFG1 StrongP The Input/Output Configuration Register 1 (IO_CFG1) con- figures the Port 1 output regulator and set the Interrupt mode for all GPIO. Bit 7: StrongP. Setting this bit increases ...
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General Purpose I/O (GPIO) 62 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 6, 12, and 24 MHz. For a complete table of the IMO registers, refer to the a ...
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Internal Main Oscillator (IMO) 7.3 Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have associated reg- ister tables showing the bit structure for that register. The bits in the tables that are ...
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CPU_SCR1 Register Address Name Bit 7 Bit 6 x,FEh CPU_SCR1 IRESS LEGEND x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # ...
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Internal Main Oscillator (IMO) 7.3.5 Related Registers OSC_CR2 Register on page 115. ■ CPU_SCR1 Register on page 137. ■ PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Internal Low Speed Oscillator (ILO) This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed Oscillator produces a 32 kHz or 1 kHz clock. For a quick reference of all PSoC ...
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Internal Low Speed Oscillator (ILO) 8.2 Register Definitions The following register is associated with the Internal Low Speed Oscillator (ILO). The register description has an associated register table showing the bit structure. The bits in the table that are grayed ...
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External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crys- tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise ...
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External Crystal Oscillator (ECO) Figure 9-2. State Transition Between ECO and ILO This transition is allowed only if the write once "ECO Exists" register bit is set. Set OSC_CR0[7] to activate the ECO, then on the next sleep interrupt, ECO ...
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Register Definitions These registers are associated with the external crystal oscillator. 9.3.1 ECO_ENBUS Register Address Name Bit 7 Bit 6 1,D2h ECO_ENBUS The ECO_ENBUS register is used to disable and enable the external crystal oscillator (ECO). Bits 2 to ...
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External Crystal Oscillator (ECO) 9.3.4 Related Registers OSC_CR0 Register, on page 113. ■ PRTxDR Registers register on page ■ PRTxIE Registers register on page 59. ■ 72 59. PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep and Watchdog registers, refer to the Summary Table of the Core Registers on page isters in address ...
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Sleep and Watchdog 10.1.1 Sleep Control Implementation Logic This section details the sleep mode logic implementation. Conditions for entering the sleep modes: Standby Mode: Set the SLEEP bit in the CPU_SCR0 register. This asserts the "sleep" signal for the sleep ...
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As shown in Figure 10-2, once the SLEEP bit is deasserted, the wakeup is initiated. The sequence is shown in the following timing diagram. The taps used in this wakeup sequence are generated based upon user configuration settings in the ...
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Sleep and Watchdog Note The T0, T1, and T2 mentioned in the SLP_CFG3 reg- ister with respect to Figure 10-2 on page 75 follows: T0: Time duration between T0 and T1 in the timing dia- ■ gram. T1: Time duration ...
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Register Definitions The following registers are associated with Sleep and Watchdog operations and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out ...
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Sleep and Watchdog 10.3.3 SLP_CFG2 Register Address Name Bit 7 Bit 6 1,ECh SLP_CFG2 The Sleep Configuration Register (SLP_CFG2) holds the configuration for I2C sleep, deep sleep, and buzz. Bits 3 and 2: ALT_Buzz[1:0]. These bits control additional selections for ...
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Timing Diagrams 10.4.1 Sleep Sequence The SLEEP bit in the CPU_SCR0 register input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence ...
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Sleep and Watchdog 10.4.2 Wakeup Sequence After asleep, the only event that wakes the system is an interrupt. The Global Interrupt Enable of the CPU Flag regis- ter does not need to be set. Any unmasked interrupt wakes the system ...
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Watchdog Timer On device boot up, the Watchdog Timer (WDT) is initially disabled. The PORS bit in the System Control register con- trols the enabling of the WDT. Upon boot, the PORS bit is initially set to '1', indicating ...
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Sleep and Watchdog 82 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Section C: TrueTouch System The configurable TrueTouch™ System section discusses the TrueTouch and analog components of the PSoC device and the registers associated with those components. This section encompasses the following chapters: TrueTouch Module on page 85. ■ I/O Analog ...
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Section C: TrueTouch System TrueTouch Register Summary The table below lists all the PSoC registers for the TrueTouch system in address order within their system resource configura- tion. The bits that are grayed out are reserved bits. If these bits ...
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TrueTouch Module This chapter presents the TrueTouch Module and its associated registers. For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 11.1 Architectural Description 11.1.1 Types of TrueTouch Approaches ...
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TrueTouch Module The circuit operates by alternately charging the sense capacitance to the internal voltage buffer level (first phase), then on the opposite phase of the clock (second phase), the analog global bus is connected to the integration capacitor while ...
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Figure 11-5. Relaxation Oscillator #2 Block Diagram Pin Enables IDAC Comparator Mux RO Clock Mux Refs 6-Bit Counter TrueTouch Logic TrueTouch IMO CSCLK 16-Bit Counter Clock Select 11.1.1.3 Successive Approximation The successive approximation method provides a fast algo- rithm for ...
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TrueTouch Module For typical capacitances, the IDAC current can be config- ured so that the average voltage on the analog global does not change. This can be done in firmware using a succes- sive approximation to find the IDAC setting ...
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Figure 11-10. Negative Charge Integration Block Diagram CSCLK and Pin Enables Reference REF_EN Buffer Vr Closed Comparator Mux Refs Mux TrueTouch Logic 16-Bit Counter CSCLK TrueTouch IMO Clock Select The initialization phase for negative CI (charge integration) is the same ...
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TrueTouch Module a. If the START output from the TIMER1 is still ’1’ - counters start incrementing again the START is ’0’ (START can become zero before comparator becomes ’1’ again) - counters stop tog- gling. To start ...
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Figure 11-13. TrueTouch Counter Block Diagram CMP0 0 ILO 1 INV CMP1 2 RLO_TIMER_TC 3 4 TIMER RLO_TIMER_IRQ 5 6 MUXBUS 7 ‘0’ INSEL[2:0] Reset No Block COUNT_EN=0 Enable PF_DONE=0 d? Yes Mode= Mode= Rising ...
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TrueTouch Module 11.2 Register Definitions The following registers are associated with the TrueTouch Module and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables ...
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CS_CR1 Register Address Name Bit 7 Bit 6 0,A1h CS_CR1 CHAIN The TrueTouch Control Register 1 (CS_CR1) contains addi- tional TrueTouch system control options. Never write to this register while the block is enabled. Bit 7: CHAIN. When this ...
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TrueTouch Module 11.2.4 CS_CR3 Register Address Name Bit 7 Bit 6 0,A3h CS_CR3 REFMUX The TrueTouch Control Register 3 (CS_CR3) contains con- trol bits primarily for the low pass filter and reference buffer. Bit 6: REFMUX. This bit selects between ...
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CS_STAT Register Address Name Bit 7 Bit 6 0,A6h CS_STAT INS COLS LEGEND # Access is bit specific. The TrueTouch Status Register (CS_STAT) controls True- Touch counter options. Status Bits The posted TrueTouch interrupts are the ...
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TrueTouch Module 11.2.9 CS_SLEW Register Address Name Bit 7 Bit 6 0,A8h CS_SLEW The TrueTouch Slew Control Register (CS_SLEW) enables and controls a fast slewing mode for the relaxation oscillator. Bits FastSlew[6:0]. This 7-bit count sets the ...
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IDAC_D Register Address Name Bit 7 Bit 6 0,FDh IDAC_D The Current DAC Data Register (IDAC_D) specifies the 8- bit multiplying factor that determines the output DAC cur- rent. 11.3 Timing Diagrams SYSCLK Block Enable Count Enable Event Count ...
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TrueTouch Module Figure 11-18. High Byte Counter Timing (RLO Clock Selected) SYSCLK Low Byte Count Enable Low Byte Clock Low Byte Count High Byte Clock High Byte Count Enable High Byte Count CS_TIMER[5:0] 03h (6-bit) RLO Clock EN Synchronized EN ...
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I/O Analog Multiplexer This chapter explains the device-wide I/O Analog Multiplexer for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated registers. For a quick reference of all registers in address order, refer to the page 187. 12.1 Architectural ...
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I/O Analog Multiplexer 12.2 Register Definitions The following registers are only associated with the Analog Bus Mux in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. Each register description has an associated register table showing the ...
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Comparators This chapter explains the Comparators for the CY8CTMG20x and CY8CTST200 PSoC devices and their associated regis- ters. For a complete table of the comparator registers, refer to the erence of all registers in address order, refer to the ...
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Comparators The comparator digital interface performs logic process- ing on one or more comparator signals, provides a latch- ing capability, and routes the result to other chip subsystems. The comparator signal is routed through a lookup table (LUT) function. The ...
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Register Definitions The following registers areassociated with the Comparators in the CY8CTMG20x and CY8CTST200 PSoC devices and are listed in address order. For a complete table of the comparator registers, refer to the page 84. Each register description has ...
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Comparators 13.2.3 CMP_CR0 Register Address Name Bit 7 Bit 6 0,7Ah CMP_CR0 The Comparator Control Register 0 (CMP_CR0) enables and configures the input range of the comparators. Bit 4: CMP1EN. This bit enables comparator 1. 13.2.4 CMP_CR1 Register Address Name ...
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Section D: System Resources The System Resources section discusses the system resources that are available for the PSoC devices and the registers associated with those resources. This section encompasses the following chapters: Digital Clocks on page 109. ■ I2C Slave ...
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Section D: System Resources System Resources Register Summary The table below lists all the registers for the system resources, in address order, within their system resource configuration. The bits that are grayed out are reserved bits. If you write these ...
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Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 0,59h PMAx_DR 0,5Ah PMAx_DR 0,5Bh PMAx_DR 0,5Ch PMAx_DR 0,5Dh PMAx_DR 0,5Eh PMAx_DR 0,5Fh PMAx_DR 0,64h PMAx_DR 0,65h PMAx_DR 0,66h PMAx_DR 0,67h PMAx_DR 0,68h PMAx_DR 0,69h PMAx_DR ...
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Section D: System Resources Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Data 0,46h EPx_CNT0 Data Valid Toggle Data 0,48h EPx_CNT0 Data Valid Toggle Data 0,4Ah EPx_CNT0 Data Valid Toggle Data 0,4Ch EPx_CNT0 Data ...
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Digital Clocks This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the ...
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Digital Clocks 14.1.2 Internal Low Speed Oscillator The Internal Low Speed Oscillator (ILO) is available as a general clock, but is also the clock source for the sleep and watchdog timers. The ILO can be disabled in deep sleep mode, ...
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Figure 14-2. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater IMO Extenal Clock SYSCLK CPUCLK IOW_ EXTCLK bit Figure 14-3. Switch from IMO to External Clock with the CPU Running with a ...
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Digital Clocks 14.2 Register Definitions The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables ...
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OUT_P0 Register Address Name Bit 7 Bit 6 1,D1h OUT_P0 P0P7D P0P7EN This register enables specific internal signals to be output to Port 0 pins. The GPIO drive modes must be specified to support the desired output mode (registers ...
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Digital Clocks view on page 70 for the proper sequence to enable the ECO. Bit 6: Disable Buzz. Setting this bit high causes the band- gap and POR/LVD systems to remain powered off continu- ously during sleep. In this case, ...
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OSC_CR2 Register Address Name Bit 7 Bit 6 1,E2h OSC_CR2 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C Bit 5 Bit 4 Bit 3 Bit 2 CLK48MEN EXTCLKEN The Oscillator Control Register 2 (OSC_CR2) configures various features ...
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Digital Clocks Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most device clocking functions. All external and internal signals, including the low speed oscillator, are ...
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I C Slave 2 This chapter explains the I C Slave block and its associated registers. The I 2 designed to implement a complete I C slave. For a complete table of the I tem Resource Registers on ...
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I2C Slave 2 The I C block controls the data (SDA) and the clock (SCL the external I C interface through direct connections to 2 two dedicated GPIO pins. When enabled, these GPIO pins are ...
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Slave Transmitter/Reciever A byte interrupt is generated. The SCL line is held low. STAR 7-Bit Address R SHIFTER M8C reads the received byte from the I2C_DR register and checks for “Own Address” and R/W. SHIFTER M8C ...
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I2C Slave by the external master through a write command and if the pointer value exceeds 1Fh, a NACK is sent. The following diagram illustrates the bus communication for a data write, a data pointer write, and a data read ...
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The following diagram illustrates an example of how the address pointers are configured in EZI2C mode. In this example, the external master sent a Start, Slave Address, and a data byte initialize both the base address pointer ...
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I2C Slave 15.3 Register Definitions The registers shown here are associated with I associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are not detailed in the register ...
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I2C_XSTAT Register Address Name Bit 7 Bit 6 0,C9h I2C_XSTAT 2 The I C Extended Status Register (I2C_XSTAT) reads enhanced feature status. All bits are read only. When the bits of I2C_XCFG are left in their reset state, the ...
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I2C Slave 15.3.5 I2C_CP Register Address Name Bit 7 Bit 6 0,CCh I2C_CP 2 The I C Current Address Pointer Register (I2C_CP) con- tains the current address value of the RAM data buffer. Note When in compatibility mode, this register ...
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I2C_BUF Register Address Name Bit 7 Bit 6 0,CFh I2C_BUF 2 The I C Data Buffer Register (I2C_BUF) is the CPU read/ write interface to the data buffer. Whenever this register is read, the data at the location pointed ...
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I2C Slave 15.3.9 I2C_CFG Register Address Name Bit 7 Bit 6 0,D6h I2C_CFG PSelect 2 The I C Configuration Register (I2C_CFG) is used to set the basic operating modes, baud rate, and selection of inter- rupts. The bits in this ...
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I C block. After enabling the I C block, wait for 3 I clocks, then configure the drive modes of the I in open drain mode. Table 15-2. Enable Operation in I2C_CFG Enable Block Operation Disabled The block ...
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I2C Slave 15.3.10 I2C_SCR Register Address Name Bit 7 Bit 6 0,D7h I2C_SCR Bus Error LEGEND # Access is bit specific. 2 The I C Status and Control Register (I2C_SCR) is used by the slave to control the flow of ...
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Bit 3: Address. This bit is set when an address is received. This consists of a Start or Restart, and an address byte. In slave mode when this status is set, firmware reads the received address from the data register ...
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I2C Slave 15.4 Timing Diagrams 15.4.1 Clock Generation 2 Figure 15-6 illustrates the I C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro- vides the baud rate selections. When the block is ...
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Status Timing Figure 15-8 illustrates the interrupt timing for byte complete, which occurs on the positive edge of the ninth clock (byte + ACK/NACK) in transmit mode and on the positive edge of the eighth clock in receive mode. ...
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I2C Slave 15.4.4 Slave Stall Timing When a byte complete interrupt occurs, the PSoC device firmware must respond with a write to the tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of ...
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Compatibility Mode Configuration In compatibility mode, the SCL, as usual, is pulled low until the CPU responds by setting the Transmit/Receive bit and for loading a byte in the I2C_DATA register (in case of transmit operation) even though IMO ...
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I2C Slave 134 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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System Resets This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for ...
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System Resets 16.2.2 Powerup External Reset Behavior The device’s core runs on chip regulated supply, so there is a time delay in powering up the core. A short XRES pulse at power up causes an external reset startup behavior. How- ...
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Register Definitions The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. The bits in the tables ...
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System Resets 16.3.2 CPU_SCR0 Register Address Name Bit 7 Bit 6 x,FFh CPU_SCR0 GIES LEGEND # Access is bit specific. Refer to register detail for additional information. XX The reset value is 10h after POR/XRES and 20h after a watchdog ...
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Timing Diagrams 16.4.1 Power On Reset A Power on Reset (POR) is triggered whenever the supply voltage is below the POR trip point. POR ends once the sup- ply voltage rises above this voltage. Refer to the LVD chapter ...
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System Resets Figure 16-4. Key Signals During POR and XRES POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+) cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8. ...
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Reset Details Timing and functionality details are summarized in for IPOR, PPOR, XRES, and WDR. Table 16-1. Reset Functionality Item IPOR (Part of POR) Reset Length Low Power (IMO Off) During Reset? Low Power Wait Following Reset? CLK32K Cycles ...
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System Resets 142 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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POR and LVD This chapter briefly discusses the Power on Reset (POR) and Low Voltage Detect (LVD) circuits and their associated regis- ters. For a complete table of the POR registers, refer to the For a quick reference of ...
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POR and LVD 17.2 Register Definitions The following registers are associated with the POR and LVD, and are listed in address order. The register descriptions below have an associated register table showing the bit structure. The bits that are grayed ...
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SPI This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI registers, refer to the Summary Table of the System Resource Registers on page isters in address order, refer to ...
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SPI 18.1.1.1 SPI Protocol Signal Definitions The SPI protocol signal definitions are located in The use of the SS_ signal varies according to the capability of the slave device. Table 18-1. SPI Protocol Signal Definitions Name Function Description Master Out ...
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Block Interrupt The SPIS block has a selection of two interrupt sources: Interrupt on TX Reg Empty (default) or interrupt on SPI Complete (same selection as the SPIM). Mode bit 1 in the Function register controls the selection. If ...
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SPI 18.2.2 SPI_RXR Register Address Name Bit 7 0,2Ah SPI_RXR The SPI Receive Data Register (SPI_RXR) is the SPI’s receive data register. A write to this register clears the RX Reg Full status bit in the Control register (SPI_CR). 18.2.2.1 ...
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Control Register 18.2.3 SPI_CR Register Address Name Bit 7 Bit 6 0,2Bh SPI_CR LSb First Overrun LEGEND # Access is bit specific. Refer to the register detail for additional information. The SPI Control Register (SPI_CR) is the SPI’s control reg- ...
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SPI Configuration Register The configuration block contains 1 register. This register must not be changed while the block is enabled. Note that the SPI Configuration register is located in bank 1 of the PSoC device’s memory map. 18.2.4 SPI_CFG Register ...
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Timing Diagrams 18.3.1 SPI Mode Timing Figure 18-3 shows the SPI modes that are typically defined These mode numbers are an encoding of two control bits: Clock Phase and Clock Polarity. Clock Phase ...
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SPI 18.3.2 SPIM Timing Enable/Disable Operation. As soon as the block is config- ured for SPIM, the primary output is the MSb or LSb of the Shift register, depending on the LSb First configuration in bit 7 of the Control ...
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Normal Operation. Typical timing for an SPIM transfer is shown in Figure 18-5 and Figure 18-6. The user initially writes a byte to transmit when TX Reg Empty status is true transmission is currently in progress, the data ...
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SPI Figure 18-6. Typical SPIM Timing in Mode 2 and 3 Free running, Setup time internal bit rate for the TX clock is CLK input Buffer write. divided by two. CLK INPUT INTERNAL CLOCK TX REG EMPTY RX REG FULL ...
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Overrun status is set if RX Reg Full is still asserted from a previous byte when a new byte is about to be loaded into the RX Buffer register. Because the RX Buffer register is imple- Figure 18-7. SPI Status ...
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SPI Figure 18-8. SPI Status Timing for Modes 2 and 3 MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge. SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) 7 MOSI 7 MISO SS_ TX REG EMPTY RX ...
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SPIS Timing Enable/Disable Operation. As soon as the block is config- ured for SPI Slave and before enabling, the MISO output is set to idle at logic 1. The Enable bit must be set and the SS_ asserted (either ...
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SPI Figure 18-10. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with first byte (by leading edge of the SCLK). SCLK (Internal) TX REG EMPTY RX REG FULL MISO SCLK (MODE 2) SCLK (MODE 3) User writes ...
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Figure 18-11 illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_ to the point at which the RX Buffer register is loaded with the received byte. ...
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SPI 160 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Programmable Timer This chapter presents the Programmable Timer and its associated registers. For a complete table of the programmable timer registers, refer to the Summary Table of the System Resource Registers on page isters in address order, refer to ...
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Programmable Timer PTDATA1 0003h PTDATA0 Clock Start One Shot Count 00h 03h TC IRQ PTDATA1 0003h PTDATA0 Clock Start One Shot Count 00h 03h TC IRQ 162 Figure 19-2. Continuous Operation Example 02h 01h 00h 03h 02h 01h TC Period ...
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Register Definitions The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are ...
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Programmable Timer 19.2.3 PT2_CFG Register Address Name Bit 7 0,B6h PT2_CFG The Programmable Timer Configuration (PT2_CFG) configures the PSoC’s programmable timer. Bit 2: CLKSEL. This bit determines if the timer runs on the 32 kHz clock or CPU clock. If ...
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Full-Speed USB This chapter explains the Full-Speed USB (Universal Serial Bus) resource and its associated registers. For a quick reference of all PSoC registers in address order, refer to the 20.1 Architectural Description The PSoC USB system resource adheres ...
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Full-Speed USB Table 20-1. Mode Encoding for Control and Non-Control Endpoints Mode Encoding SETUP Disable 0000 Ignore NAK IN/OUT 0001 Accept Status OUT Only 0010 Accept STALL IN/OUT 0011 Accept Reserved 0100 Ignore ISO OUT 0101 Ignore Status IN Only ...
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The PMA's purpose is to manage the potentially conflicting SRAM access requests from the M8C and the USB SIE. From a performance standpoint, the PMA guarantees that a continuous stream of move instructions (see ahead), are serviced by the PMA ...
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Full-Speed USB For a USB IN transaction, the USB SIE is reading data from the PMA and sending the data to the USB host. The follow- ing steps must be used to set up a PMA channel for a USB ...
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Suspend mode.) This condition is detected by monitoring the Bus Activity bit in the USB_CR1 register. This bit must be polled periodically reads high (bus activity present), it must be ...
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Full-Speed USB Figure 20-2. Transceiver and Regulator Block Diagram VOLTAGE REGULATOR 5V 3.3V TEN TD RECEIVERS PDN RD DPO RSE0 DMO 170 S1 1.5K PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C PS2 Pull ...
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Register Definitions The following registers are related to Full-Speed USB in the PSoC device. For a complete table of the Full-Speed USB regis- ters, refer to the Registers table Summary Table of the System Resource Registers on page out ...
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Full-Speed USB 20.3.3 USBIO_CR0 Register Address Name Bit 7 Bit 6 0,34h USBIO_CR0 TEN TSE0 The USB I/O Control Register 0 (USBIO_CR0) is used for manually transmitting on the USB D+ and D- pins, or read- ing the differential receiver. ...
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EP0_CR Register Address Name Bit 7 Setup 0,36h EP0_CR IN Received Received The Endpoint Control Register (EP0_CR) is used to config- ure endpoint 0. Because both firmware and the SIE are allowed to write to the Endpoint 0 Control ...
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Full-Speed USB 20.3.6 EP0_CNT Register Address Name Bit 7 Bit 6 0,37h EP0_CNT Data Toggle Data Valid The Endpoint 0 Count Register (EP0_CNT) is used to con- figure endpoint 0. Whenever the count updates from a setup or OUT transac- ...
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EPx_CNT1 Register Address Name Bit 7 Bit 6 0,41h EP1_CNT1 0,43h EP2_CNT1 0,45h EP3_CNT1 0,47h EP4_CNT1 0,49h EP5_CNT1 0,4Bh EP6_CNT1 0,4Dh EP7_CNT1 0,4Fh EP8_CNT1 The Endpoint Count Register 1 (EPx_CNT1) sets or reports the number of bytes in a ...
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Full-Speed USB 20.3.9 EPx_CNT0 Register Address Name Bit 7 0,40h EP1_CNT0 Data Toggle Data Valid 0,42h EP2_CNT0 Data Toggle Data Valid 0,44h EP3_CNT0 Data Toggle Data Valid 0,46h EP4_CNT0 Data Toggle Data Valid 0,48h EP5_CNT0 Data Toggle Data Valid 0,4Ah ...
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EPx_CR0 Register Address Name Bit 7 Bit 6 1,54h EP1_CR0 Stall 1,55h EP2_CR0 Stall 1,56h EP3_CR0 Stall 1,57h EP4_CR0 Stall 1,58h EP5_CR0 Stall 1,59h EP6_CR0 Stall 1,5Ah EP7_CR0 Stall 1,5Bh EP8_CR0 Stall The Endpoint Control Register 0 (EPx_CR0) is ...
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Full-Speed USB 20.3.11 PMAx_WA Register Address Name Bit 7 Bit 6 1,34h PMA0_WA 1,35h PMA1_WA 1,36h PMA2_WA 1,37h PMA3_WA 1,38h PMA4_WA 1,39h PMA5_WA 1,3Ah PMA6_WA 1,3Bh PMA7_WA 1,44h PMA8_WA 1,45h PMA9_WA 1,46h PMA10_WA 1,47h PMA11_WA 1,48h PMA12_WA 1,49h PMA13_WA 1,4Ah ...
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PMAx_DR Register Address Name Bit 7 Bit 6 0,58h PMA0_DR 0,59h PMA1_DR 0,5Ah PMA2_DR 0,5Bh PMA3_DR 0,5Ch PMA4_DR 0,5Dh PMA5_DR 0,5Eh PMA6_DR 0,5Fh PMA7_DR 0,64h PMA8_DR 0,65h PMA9_DR 0,66h PMA10_DR 0,67h PMA11_DR 0,68h PMA12_DR 0,69h PMA13_DR 0,6Ah PMA14_DR 0,6Bh ...
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Full-Speed USB 20.3.13 PMAx_RA Register Address Name Bit 7 Bit 6 1,3Ch PMA0_RA 1,3Dh PMA1_RA 1,3Eh PMA2_RA 1,3Fh PMA3_RA 1,40h PMA4_RA 1,41h PMA5_RA 1,42h PMA6_RA 1,43h PMA7_RA 1,4Ch PMA8_RA 1,4Dh PMA9_RA 1,4Eh PMA10_RA 1,4Fh PMA11_RA 1,50h PMA12_RA 1,51h PMA13_RA 1,52h ...
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IMO_TR1 Register Address Name Bit 7 Bit 6 1,FAh IMO_TR1 INTERNAL Register – The Internal Main Oscillator Trim Register 1 (IMO_TR1) fine tunes the IMO frequency. For information on the other IMO trim register (IMO_TR) see the Internal Main ...
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Full-Speed USB 182 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Section E: Registers The Registers section discusses the registers of the PSoC device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in ...
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Section E: Registers Register Map Bank 0 Table: User Space PRT0DR 00 RW 188 EP1_CNT0 PRT0IE 01 RW 189 EP1_CNT1 02 EP2_CNT0 03 EP2_CNT1 PRT1DR 04 RW 188 EP3_CNT0 PRT1IE 05 RW 189 EP3_CNT1 06 EP4_CNT0 07 EP4_CNT1 PRT2DR 08 ...
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Register Map Bank 1 Table: Configuration Space PRT0DM0 00 RW 259 PMA4_RA PRT0DM1 01 RW 260 PMA5_RA 02 PMA6_RA 03 PMA7_RA PRT1DM0 04 RW 259 PMA8_WA PRT1DM1 05 RW 260 PMA9_WA 06 PMA10_WA 07 PMA11_WA PRT2DM0 08 RW 259 PMA12_WA ...
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Section E: Registers 186 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C [+] Feedback ...
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Register Reference This chapter is a reference for all the PSoC device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the PSoC registers are in the Register Definitions section of each chapter. ...
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PRTxDR 0,00h 21.3 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi- cates that the register can be accessed in Bank 0 ...
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PRTxIE Port Interrupt Enable Registers Individual Register Names and Addresses: PRT0IE : 0,01h PRT1IE : 0,05h PRT4IE : 0,11h 7 6 Access : POR Bit Name These registers enable or disable interrupts from individual GPIO pins. The upper nibble ...
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SPI_TXR 0,29h 21.3.3 SPI_TXR SPI Transmit Data Register Individual Register Names and Addresses: SPI_TXR : 0,29h 7 6 Access : POR Bit Name This register is the SPI’s transmit data register. For additional information, refer to the Register Definitions on ...
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SPI_RXR SPI Receive Data Register Individual Register Names and Addresses: SPI_RXR : 0,2Ah 7 6 Access : POR Bit Name This register is the SPI’s receive data register. For additional information, refer to the Register Definitions on page 147 ...
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SPI_CR 0,2Bh 21.3.5 SPI_CR SPI Control Register Individual Register Names and Addresses: SPI_CR : 0,2Bh 7 6 Access : POR Bit Name LSb First Overrun This register is the SPI control register. The LSb ...
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USB_SOF0 USB Start-of-Frame Register 0 Individual Register Names and Addresses: USB_SOF0 : 0,31h 7 6 Access : POR Bit Name This register is a USB Start-of-Frame register 0. For additional information, refer to the Register Definitions on page 171 ...
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USB_SOF1 0,32h 21.3.7 USB_SOF1 USB Start-of-Frame Register 1 Individual Register Names and Addresses: USB_SOF1 : 0,32h 7 6 Access : POR Bit Name This register is a USB Start-of-Frame register 1. In the table above, note that reserved bits are ...
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USB_CR0 USB Control Register 0 Individual Register Names and Addresses: USB_CR0 : 0,33h 7 6 Access : POR Bit Name USB Enable This register is a USB control register 0. For additional information, refer to the ...
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USBIO_CR0 0,34h 21.3.9 USBIO_CR0 USB I/O Control Register 0 Individual Register Names and Addresses: USBIO_CR0 : 0,34h 7 6 Access : POR Bit Name TEN TSE0 This register is a USBIO manual control register ...
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USBIO_CR1 USB I/O Control Register 1 Individual Register Names and Addresses: USBIO_CR1 : 0,35h 7 6 Access : POR Bit Name IOMode Drive Mode This register is a USBIO manual control register 1. ...
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EP0_CR 0,36h 21.3.11 EP0_CR Endpoint 0 Control Register Individual Register Names and Addresses: EP0_CR : 0,36h 7 6 Access : POR Bit Name Setup IN Received Received This register is an endpoint 0 control ...
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EP0_CNT Endpoint 0 Count Register Individual Register Names and Addresses: EP0_CNT : 0,37h 7 6 Access : POR Bit Name Data Toggle Data Valid The Endpoint 0 Count register (EP0_CNT) configures endpoint 0. ...
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EP0_DRx 0,38h 21.3.13 EP0_DRx Endpoint 0 Data Registers Individual Register Names and Addresses: EP0_DR0 : 0,38h EP0_DR1 : 0,39h EP0_DR4 : 0,3Ch EP0_DR5 : 0,3Dh 7 6 Access : POR Bit Name These registers are endpoint 0 data registers. For ...