CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 117

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

This chapter explains the I
designed to implement a complete I
tem Resource Registers on page
Reference chapter on page
15.1
The I
two-wire I
vides I
firmware compatible with the previous generation of I
are configurable to implement significant flexibility for both internal and external interfacing.
Basic I
■
■
■
■
■
■
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
15. I
Slave, transmitter, and receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for clock rates of up to 400 kHz
7- or 10-bit addressing (through firmware support)
SMBus operation (through firmware support)
2
C slave enhanced communications block is a serial-to-parallel processor, designed to interface the PSoC device to a
2
2
C-specific support for status detection and generation of framing bits. By default, the I
C features include:
2
To/From
C serial communications bus. To eliminate the need for excessive CPU intervention and overhead, the block pro-
GPIO
Architectural Description
Pins
2
C Slave
SDA_OUT
SCL_OUT
2
C Slave block and its associated registers. The I
187.
SDA_IN
SCL_IN
I2C_EN
106. For a quick reference of all PSoC registers in address order, refer to the
2
C slave. For a complete table of the I
Figure 15-1. I
HW Addr Cmp
Plus Features
Configuration
I2C Core
I2C_XSTAT
I2C Basic
I2C_ADDR
I2C_XCFG
I2C_CFG
I2C_SCR
I2C_DR
2
C slave functionality. However, this module provides new features that
2
C Block Diagram
Enhanced features of the I
include:
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I2C Plus
Support for 7-bit hardware address compare
Flexible data buffering schemes
A "no bus stalling" operating mode
A low power bus monitoring mode
Slave
2
C registers, refer to the
2
Buffer Module
C communications block is a serial processor
32 Byte RAM
CPU Port
Buffer Ctl
I2C_BUF
MCU_BP
MCU_CP
I2C_BP
I2C_CP
2
2
C Slave Enhanced module is
C Slave Enhanced module
Summary Table of the Sys-
SYSCLK
STANDBY
Register
117
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