CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 277

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

21.4.18 ECO_CFG
This register provides ECO status and control information.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 71
Bits
2
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
ECO_CFG : 1,E1h
Access : POR
Bit Name
in the External Crystal Oscillator chapter.
Name
ECO_LPM
ECO_EXW
ECO_EX
External Oscillator Trim Configuration Register
7
6
Description
This bit enables the ECO lower power mode.
This is a status bit that indicates that the ECO_EX bit was previously written to.
When this bit is a '1', this indicates that the ECO_CONFIG register was written to and is now locked.
When this bit is a '0', the register was not written to since the last reset event.
The ECO Exists bit is a flag to the hardware indicating that an external crystal oscillator exists in the
system.If the bit is '0', a switch-over to the ECO is locked out by hardware. If the bit is '1', hardware
allows the firmware to freely switch between the ECO and ILO. It must be written as early as possible
after a Power On Reset (POR) or External Reset (XRES) event.
5
4
3
ECO_LPM
RW : 0
2
1,E1h
ECO_EXW
RW : 0
ECO_CFG Register on
1
ECO_CFG
ECO_EX
RW : 0
1,E1h
0
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