CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 119

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

15.2.2
When EZI2C mode is configured with the Buffer Mode bit of
the I2C_XCFG register, both the master and slave must use
a predefined communication protocol. In this protocol, the
I
external master controls the read and write addresses to the
32-byte RAM buffer. The external master reads and writes
to the RAM buffer are independent of the CPU reads and
writes to the RAM buffer, so conceptually, it appears as a
dual port RAM buffer. Higher level protocols, such as polling
or semaphore methods, are used to ensure data synchroni-
zation and integrity. Conceptually, data is always available
in this mode so the bus never stalls except in I
mode.
The RAM buffer interfaces contain separate address point-
ers, I2C_BP and I2C_CP, that are set with the first data byte
of a write operation. When the external master writes one or
more bytes, the first data byte is always the base address
pointer value. This value gets written to both the base
address pointer, I2C_BP, and the current address pointer,
I2C_CP. The byte after the base address pointer is written
into the location pointed to by the current address pointer
value contained in I2C_CP.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
2
STAR
C slave operates as a RAM buffer interface, in which the
T
Slave Transmitter/Reciever
7-Bit Address
1
EZI2C Mode
A byte interrupt is generated.
The SCL line is held low.
7
the I2C_DR register and checks for
M8C reads the received byte from
R/W
8
“Own Address” and R/W.
M8C writes the byte to transmit
SHIFTER
to the I2C_DR register.
SHIFTER
M8C writes (ACK) to
I2C_SCR register.
Figure 15-3. Slave Operation
(ACK | TRANSMIT) to
ACK
2
I2C_SCR register.
C sleep
M8C writes
ACK
9
complete. The SCL line is held low.
1
1
The third byte (second data byte) is written to the current
address pointer value, I2C_CP, plus one and so on. This
current address pointer, I2C_CP, increments for each byte
read or written, but is reset to the base address pointer
value at the beginning of each new write or read operation
(following a start command).
For example, if the base address pointer, I2C_BP, is set to
4, a read operation begins to read data at location 4 and
continues sequentially until the host completes the read
operation. So, if the base address pointer is set to 4, each
read operation resets the data pointer to 4 and reads
sequentially from that location. This is true whether single or
multiple read operations are performed. The base address
pointer is not changed until a new write operation initiates.
If the I
address boundary, 32 bytes, the data is discarded and does
not affect any RAM inside or outside the designated RAM
area. You cannot read data outside the allowed range. Any
read requests by the master outside the allowed range
result in the return of invalid data. If the RAM address is sent
An interrupt is generated on byte
An interrupt is generated on a
complete byte + ACK/NACK.
8-Bit Data
8-Bit Data
The SCL line is held low.
2
C master attempts to write data past the RAM
7
7
M8C reads the received byte from
8
8
the I2C_DR register.
ACK/NACK
SHIFTER
9
M8C issues ACK/NACK
command with a write to
the I2C_SCR register.
command to I2C_SCR to release the bus.
ACK/NACK
register and then writes a TRANSMIT
M8C writes a new byte to the I2C_DR
says end-of-data.
NACK = Master
ACK = Master wants to
9
read another byte.
NACK = Slave
says no more.
transmit another
byte or STOP.
STOP
Master may
receive more.
ACK = OK to
STOP
I2C Slave
119
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