CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 227

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

21.3.39 I2C_XSTAT
This register reads enhanced feature status.
When the bits of the
use. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section
below. Always write reserved bits with a value of ‘0’. For additional information, refer to the
in the I2C Slave chapter.
Bit
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
I2C_XSTAT : 0,C9h
Access : POR
Bit Name
Dir
Slave Busy
Name
I
2
C Extended Status Register
7
I2C_XCFG
register are left in their reset state, the block is in compatibility mode and this register is not in
6
Description
This bit indicates the direction of the current transfer. A ’1’ indicates a master read, and a ‘0’ indicates
a master write. It is only valid when the Slave Busy bit (bit 0) is set to a ‘1’.
This bit is set upon a hardware compare and is reset upon the following stop signal. Poll this bit to
determine when the slave is busy and the buffer module is being accessed.
5
4
0,C9h
3
2
Register Definitions on page 122
0,D0h
R : 0
Dir
1
I2C_XSTAT
Slave Busy
0,C9h
R : 0
0
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