CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 94

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

11.2.4
The TrueTouch Control Register 3 (CS_CR3) contains con-
trol bits primarily for the low pass filter and reference buffer.
Bit 6: REFMUX. This bit selects between VREF and REFHI
for the reference buffer input.
Bit 5: REFMODE. This bit is used for manual connection of
the reference buffer to the analog global bus. If either the
CI_EN or RO_EN bits are set high in the CS_CR2 register,
this bit has no effect.
11.2.5
The TrueTouch Counter Low Byte Register (CS_CNTL) con-
tains the current count for the low byte counter.
11.2.6
The TrueTouch Counter High Byte Register (CS_CNTH)
contains the current count value for the high byte counter.
TrueTouch Module
94
0,A3h
0,A4h
0,A5h
Address
Address
Address
CS_CR3
CS_CNTL
CS_CNTH
CS_CR3 Register
CS_CNTL Register
CS_CNTH Register
Name
Name
Name
Bit 7
Bit 7
Bit 7
REFMUX
Bit 6
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
REFMODE
Bit 5
Bit 5
Bit 5
REF_EN
Bit 4
Bit 4
Bit 4
Data[7:0]
Data[7:0]
Bit 4: REF_EN. This bit enables the reference buffer to
drive to the analog global bus.
Bits 3 and 2: LPFilt[1:0]. These bits control the time con-
stant of the low pass filter that connect to the analog bus.
Bits 1 and 0: LPF_EN[1:0]. These bits are used to connect
a low pass filter into the input of either comparator channel.
For additional information, refer to the
page
Bits 7 to 0: Data[7:0]. This value contains the current
count for the counter low block. Stop this block to read a
valid value.
For additional information, refer to the
page
Bits 7 to 0: Data[7:0]. This value contains the current
count for the counter high block. Stop this block to read a
valid value.
For additional information, refer to the
page
214.
215.
216.
Bit 3
Bit 3
Bit 3
LPFilt[1:0]
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
LPF_EN[1:0]
CS_CNTH register on
CS_CNTL register on
CS_CR3 register on
Bit 0
Bit 0
Bit 0
Access
RW : 00
Access
Access
RO : 00
RO : 00
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