CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 154

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

Status Generation and Interrupts. There are four status
bits in an SPI block: TX Reg Empty, RX Reg Full, SPI Com-
plete, and Overrun.
TX Reg Empty indicates that a new byte can be written to
the TX Buffer register. When the block is enabled, this status
bit is immediately asserted. This status bit is cleared when
the user writes a byte of data to the TX Buffer register. TX
Reg Empty is a control input to the state machine and, if a
transmission is not already in progress, the assertion of this
control signal initiates one. This is the default SPIM block
interrupt. However, an initial interrupt is not generated when
the block is enabled. The user must write a byte to the TX
Buffer register and that byte must be loaded into the shifter
before interrupts generated from the TX Reg Empty status
bit are enabled.
RX Reg Full is asserted on the edge that captures the eighth
bit of receive data. This status bit is cleared when the user
reads the RX Buffer register (DR2).
SPI Complete is an optional interrupt and is generated when
eight bits of data and clock have been sent. In modes 0 and
1, this occurs one-half cycle after RX Reg Full is set;
because in these modes, data is latched on the leading
edge of the clock and there is an additional one-half cycle
remaining to complete that clock. In modes 2 and 3, this
occurs at the same edge that the receive data is latched.
This signal may be used to read the received byte or it may
be used by the SPIM to disable the block after data trans-
mission is complete.
SPI
154
INTERNAL CLOCK
clock is CLK input
internal bit rate
divided by two.
Free running,
TX REG EMPTY
SCLK (MODE 2)
SCLK (MODE 3)
RX REG FULL
CLK INPUT
User writes first
Buffer register.
byte to the TX
MOSI
Buffer write.
Figure 18-6. Typical SPIM Timing in Mode 2 and 3
Setup time
for the TX
First input bit
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
is latched.
with the first byte.
D7
Shifter is loaded
First shift.
D6
D5
User writes next
Buffer register.
byte to the TX
edge and is latched
data is valid on this
Last bit of received
into RX Buffer.
D2
D1
D0
Shifter is loaded
with the next
byte.
D7
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