CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 128

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

15.3.10
The I
the slave to control the flow of data bytes and to keep track
of the bus state during a transfer.
This register contains status bits to determine the state of
the current I
actions for the next byte transfer. At the end of each byte
transfer, the I
ler and stalls the I
until the PSoC device intervenes with the next command.
This register may be read as many times as necessary; but
on a subsequent write to this register, the bus stall is
released and the current transfer continues.
There are five status bits: Byte Complete, LRB, Address,
Stop Status, and Bus Error. These bits have Read/Clear
(RC) access, which means that they are set by hardware but
may be cleared by a write of ‘0’ to the bit position. Under cer-
tain conditions, status is cleared automatically by the hard-
ware.
There are two control bits: Transmit and ACK. These bits
have RW access and may be cleared by hardware.
Bit 7: Bus Error. The Bus Error status detects misplaced
Start or Stop conditions on the bus. These may be due to
noise, rogue devices, or other devices that are not yet syn-
chronized with the I
ification, all compatible devices must reset their interface
upon a received Start or Stop. This is a natural thing to do in
slave mode because a Start initiates an address reception
and a Stop idles the slave.
A bus error is defined as follows. A Start is only valid if the
block is idle or a slave receiver is ready to receive the first bit
of a new byte after an ACK. Any other timing for a Start con-
dition sets the Bus Error bit. A Stop is only valid if the block
is idle or a slave receiver is ready to receive the first bit of a
new byte after an ACK. Any other timing for a Stop condition
sets the Bus Error bit.
Bit 5: Stop Status. Stop status is set upon detection of an
I
remains set until a ‘0’ is written back to it by the firmware.
This bit may only be cleared if the Byte Complete status bit
is set. If the Stop Interrupt Enable bit is set, an interrupt is
also generated upon Stop detection. It is never automatically
cleared. Using this bit, a slave can distinguish between a
previous Stop or Restart upon a given address byte inter-
rupt.
I2C Slave
128
2
0,D7h
LEGEND
# Access is bit specific.
C Stop condition. This bit is sticky, which means that it
Address
2
C Status and Control Register (I2C_SCR) is used by
I2C_SCR
2
I2C_SCR Register
2
C transfer, and control bits to determine the
Name
C hardware interrupts the M8C microcontrol-
2
C bus on the subsequent low of the clock,
2
C bus traffic. According to the I
Bus Error
Bit 7
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Status
Bit 5
Stop
2
C spec-
Bit 4
ACK
The selections are shown in the following table:
Bit 4: ACK.
This control bit defines the acknowledge data bit that is
transmitted out in response to a received byte. When receiv-
ing, a byte complete interrupt is generated after the eighth
data bit is received. Upon the subsequent write to this regis-
ter to continue (or terminate) the transfer, the state of this bit
determines the next transmitted data bit. It is active high . A
‘1’ sends an ACK and a ‘0’ sends a NACK. A slave receiver
sends a NACK to inform the master that it cannot receive
any more bytes.
7
5
4
3
2
1
0
Bit Access
RC
RC
RW
RC
RW
RC
RC
Address
Bit 3
Bus Error
1 = A misplaced Start or Stop condition was detected.
This status bit must be cleared by firmware with a write of ‘0’
to the bit position. It is never cleared by the hardware.
Stop Status
1 = A Stop condition was detected.
This status bit must be cleared by firmware with a write of ‘0’
to the bit position. It is never cleared by the hardware.
ACK: Acknowledge Out
0 = NACK the last received byte.
1 = ACK the last received byte.
This bit is automatically cleared by hardware upon the fol-
lowing byte complete event.
Address
1 = The transmitted or received byte is an address.
This status bit must be cleared by firmware with a write of ‘0’
to the bit position.
Transmit
0 = Receive Mode.
1 = Transmit Mode.
This bit is set by firmware to define the direction of the byte
transfer.
Any Start detect automatically clears this bit.
LRB: Last Received Bit
The value of the ninth bit in a transmit sequence, which is
the acknowledge bit from the receiver.
0 = Last transmitted byte was ACK’ed by the receiver.
1 = Last transmitted byte was NACK’ed by the receiver.
Any Start detect automatically clears this bit.
Byte Complete
Transmit Mode:
1 = 8 bits of data have been transmitted and an ACK or
NACK has been received.
Receive Mode:
1 = 8 bits of data have been received.
Any Start detect automatically clears this bit.
Transmit
Bit 2
Bit 1
LRB
Description
Complete
Bit 0
Byte
Access
# : 00
[+] Feedback