CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 74

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

10.1.1
This section details the sleep mode logic implementation.
Conditions for entering the sleep modes:
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10.1.1.1
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Sleep and Watchdog
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Standby Mode: Set the SLEEP bit in the CPU_SCR0 register. This asserts the "sleep" signal for the sleep controller.
I2C_USB Mode: Set the I2C_ON bit in the SLP_CFG2 register and then set the SLEEP bit in the CPU_SCR0 register.
Another way to enter I2C_USB sleep mode is to set the USB Enable bit in the USB_CR0 register and then set the SLEEP
bit in the CPU_SCR0 register. This asserts the sleep signal for the sleep controller and also the I2CEnable signal to the
power system.
The I2C block works in I2C_USB sleep mode only to wake up the system. That is, when the device is in sleep, I2C can
detect a start condition and receive an address. If the address matches, I2C generates an interrupt and wakes the system
(refer to
you are in the middle of I2C transactions), I2C does not work and will send NACKs. I2C can only detect a start condition
and collect an 8-bit address then wake the system through an interrupt during I2C sleep mode. Therefore it is recom-
mended to check the bus status in the I2C_XSTAT register before putting the device to sleep if there is any I2C data
transfer.
Deep Sleep Mode: Configure the I2C_ON bit in the SLP_CFG2 register to 0, then USB Enable bit in the USB_CR0 regis-
ter to '0' and the X32ON bit in OSC_CR0 to '0'. Set the LSO_OFF bit in the SLP_CFG2 register and then set the "SLEEP"
bit in the CPU_SCR0 register. This enables the LSO_OFF signal to power down the LSO. The system enters into deep
sleep mode. One point to note here is to not set the X32ON bit to '1' without setting the ECO_EX (ECO exists) bit in the
ECO_CFG (1,E1h) register to a '1'. If you do so, the deep sleep mode is not entered, but clk32K is also not running. This
implies that the sleep timer interrupt or the programmable timer interrupt cannot occur.
Waking up from standby mode is by an interrupt, which can be a sleep timer interrupt, a GPIO interrupt, a 16-bit program-
mable timer 0 interrupt, or a USB interrupt.
For the device, the wakeup from I2C_USB sleep mode can be by an I2C interrupt in addition to a sleep timer interrupt, a
programmable timer 0 interrupt, a GPIO interrupt, or a USB interrupt.
For the device, the wakeup from deep sleep mode can be by either a GPIO interrupt or a USB interrupt.
In standby mode during buzz, if the external supply falls below the LVD limit, an LVD interrupt occurs and initiates the
wakeup sequence.
In standby mode, if watchdog reset occurs, it first initiates the wakeup sequence. Once the wakeup is done, it resets the
system.
Power Modes on page
Sleep Control Implementation Logic
Wakeup Logic
141). If you put the device to sleep again while these transactions are ocurring (i.e., when
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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