CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 231

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

21.3.43 CPU_BP
This register contains the base address value of the RAM data buffer.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
I2C Slave chapter.
Bit
4:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CPU_BP : 0,CDh
Access : POR
Bit Name
CPU Base Pointer[4:0]
Name
CPU Base Address Pointer Register
7
6
Description
This register value is completely controlled by I/O writes by the CPU. Firmware routines must set this
register. Similar to the I2C_BP_WR, the value of this register sets the starting address for the data
location being written to or read from. When this register is written, the current address pointer
CPU_CP is also updated with the same value. The first read or write from/to the I2C_ BUF register
starts at this address. The location of the data in subsequent read or writes is determined by the
CPU_CP register value, which auto increments after each read or write. Firmware makes certain that
the slave device always has valid data or the data is read before overwritten.
5
0,CDh
4
3
CPU Base Pointer[4:0]
Register Definitions on page 122
RW : 00
2
1
0,CDh
CPU_BP
0
in the
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