CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 35

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

The IRAMDIS bit allows the preservation of variables even if
a watchdog reset (WDR) occurs. The IRAMDIS bit is reset
by all system resets except watchdog reset. Therefore, this
bit is only useful for watchdog resets and not general resets.
Table 3-5. SRAM Map Post SWBootReset (00h)
Address F8h is the return code byte for all SROM functions
(except Checksum and TableRead); for this function, the
only acceptable values are 00h, 02h, and 06h. Address FCh
is the fail count variable. After POR (Power on Reset),
WDR, or XRES (External Reset), the variable is initialized to
00h by the SROM. Each time the Checksum fails, the fail
count is incremented. Therefore, if it takes two passes
through SWBootReset to get a good Checksum, the fail
count is 01h.
3.1.2.2
The ReadBlock function is used to read 128 contiguous
bytes from Flash: a block. The device has 32 KB of Flash
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Address
0x0_
0x1_
0x2_
0x3_
0x4_
0x5_
0x6_
0x7_
0x8_
0x9_
0xA_
0xB_
0xC_
0xD_
0xE_
0xF_
0x00
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0x00
0x00
0x00
0x00
0x00
0x02
0x06
0
8
ReadBlock Function
0x00
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Xx
1
9
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A
2
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B
3
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0xn
C
4
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5
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6
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7
F
and has two hundred fifty-six 128-byte blocks. Valid block
IDs are 0x00 to 0xFF.
Table 3-6. Flash Memory Organization
The first thing the ReadBlock function does is check the pro-
tection bits to determine if the wanted BLOCKID is readable.
If read protection is turned on, the ReadBlock function exits
setting the accumulator and KEY2 back to 00h. KEY1 has a
value of 01h indicating a read failure.
If read protection is not enabled, the function reads 128
bytes from the Flash using a ROMX instruction and stores the
results in SRAM using an MVI instruction. The 128 bytes are
stored in SRAM, beginning at the address indicated by the
value of the POINTER parameter. When the ReadBlock
completes successfully, the accumulator, KEY1, and KEY2
has a value of 00h.
Note An MVI [expr], A stores the Flash block contents
in SRAM meaning that you can use the MVW_PP register to
indicate which SRAM pages receive the data.
Table 3-7. ReadBlock Parameters (01h)
3.1.2.3
The WriteBlock function stores data in the Flash. No verifi-
cation of the data is performed, but execution time is about
1 ms less than the WriteAndVerify function. The WriteAnd-
Verify function is the recommended method for altering the
data in one Block of Flash
page
Flash. This is a two-step process, the first step is to load the
page latch with 128 bytes of data and it is followed by the
programming of the corresponding block of Flash. No erase
is needed before WriteBlock.
If write protection is turned on, then the WriteBlock function
exits, setting the accumulator and KEY2 back to 00h. KEY1
has a value of 01h, indicating a write failure. Write protection
is set when the PSoC device is programmed externally and
cannot be changed through the SSC function.
The BLOCKID of the Flash block, where the data is stored,
must be determined and stored at SRAM address FAh. Valid
block IDs are 0x00 to 0xFF.
CY8CTMG200,
CY8CTST200
MVW_PP
KEY1
KEY2
BLOCKID
POINTER
PSoC Device
Name
37). Data moves 128 bytes at a time from SRAM to
0,D5h
0,F8h
0,F9h
0,FAh
0,FBh
Address
WriteBlock Function
32 KB
Amount of
Flash
Register
RAM
RAM
RAM
RAM
Type
(see “WriteAndVerify Function” on
2K Bytes
Amount of
MVI write page pointer register.
3Ah.
Stack Pointer value+3, when SSC is
executed.
Flash block number.
Addresses in SRAM to store returned
data.
SRAM
Supervisory ROM (SROM)
256
Number of
Description
per Bank
Blocks
1
Number of
Banks
[+] Feedback
35