CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 124

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

15.3.5
The I
tains the current address value of the RAM data buffer.
Note When in compatibility mode, this register is not in use.
Bits 4 to 0: I2C Current Pointer[4:0]. This register gets
set at the same time and with the same value as the
Register. After each completed data byte of the current I
transaction, the value of this register is incremented by one.
15.3.6
The CPU Base Address Pointer Register (CPU_BP) con-
tains the base address value of the RAM data buffer.
Note When in compatibility mode, this register is not in use.
Bits 4 to 0: CPU Base Pointer[4:0]. This register value is
completely controlled by I/O writes by the CPU. Firmware
routines must set this register. As with the I2C_BP, the value
of this register sets the starting address for the data location
being written or read. When this register is written, the cur-
rent address pointer, CPU_CP, is also updated with the
same value.
15.3.7
The CPU Current Address Pointer Register (CPU_CP) con-
tains the current address value of the RAM data buffer.
Note When in compatibility mode, this register is not in use.
I2C Slave
124
0,CCh
0,CDh
0,CEh
Address
Address
Address
2
C Current Address Pointer Register (I2C_CP) con-
I2C_CP
CPU_BP
CPU_CP
I2C_CP Register
CPU_BP Register
CPU_CP Register
Name
Name
Name
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 5
Bit 5
I2C_BP
2
C
Bit 4
Bit 4
Bit 4
The value rolls over to 0x00 when the master writes the
32nd byte.
The value of this register always determines the location
that read or write data comes from or is written to. This reg-
ister is set to the value contained in the
every start condition detected in the bus.
For additional information, refer to the
page
The first read or write from/to the I2C_ BUF register start at
this address. The location of the data in subsequent read or
writes is determined by the CPU_CP register value, which
auto increments after each read or write. Firmware makes
certain that the slave device always has valid data or the
data is read before overwritten.
For additional information, refer to the
page
Bits 4 to 0: CPU Current Pointer[4:0]. This register is set
at the same time and with the same value as the
Register. Whenever the
read, the CPU_CP increments automatically.
For additional information, refer to the
page
230.
231.
232.
Bit 3
Bit 3
Bit 3
I2C Current Pointer[4:0]
CPU Base Pointer[4:0]
CPU Current Pointer[4:0]
Bit 2
Bit 2
Bit 2
I2C_BUF Register
Bit 1
Bit 1
Bit 1
CPU_CP register on
CPU_BP register on
I2C_BP Register
I2C_CP register on
Bit 0
Bit 0
Bit 0
is written or
Access
Access
RW : 00
CPU_BP
R : 00
Access
R : 00
on
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