LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 11

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
1.2
1.3
1.4
16-bit SRAM I/F
Wakup Indicator
PME
FIFO_SEL
IRQ
This section provides an overview of each of these functional blocks as shown in
Block
The LAN9211 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent
Interface) port internal to the LAN9211. The MAC CSR's also provide a mechanism for accessing the
PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
Internal Block Overview
10/100 Ethernet PHY
10/100 Ethernet MAC
Diagram".
Host Bus Interface
PIO Controller
Management
Controller
GP Timer
Interrupt
Power
(HBI)
Figure 1.2 Internal Block Diagram
Configurable RX FIFO
Configurable TX FIFO
RX Status FIFO
TX Status FIFO
Core Regulator
2kB to 14kB
2kB to 14kB
3.3V to 1.8V
DATASHEET
+3.3V
11
25MHz
PLL
Ethernet
Buffer - 128 bytes
Buffer - 2K bytes
MIL - RX Elastic
Offload Engine
Offload Engine
MIL - TX Elastic
RX Checksum
10/100
TX Checksum
MAC
(Optional)
EEPROM
EEPROM
Controller
Ethernet
10/100
PHY
Figure 1.2, "Internal
Revision 2.7 (03-15-10)
LAN