LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 83

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
5.3.4
30:26
12:11
BITS
2-0
31
25
24
23
22
21
20
19
18
17
16
15
14
13
10
9
8
7
6
5
4
3
Software Interrupt (SW_INT_EN)
Reserved
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable (RXDFH_INT_EN).
Reserved
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt (RXD_INT).
GP Timer (GPT_INT_EN)
PHY (PHY_INT_EN)
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
Reserved
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
INT_EN—Interrupt Enable Register
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of
the interrupt source regardless of whether the source is enabled as an interrupt in this register.
Offset:
DESCRIPTION
5Ch
DATASHEET
83
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Revision 2.7 (03-15-10)
DEFAULT
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-