LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 99

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
5.3.22
31:24
23:16
BITS
15:8
7:4
3
2
1
Reserved
Automatic Flow Control High Level (AFC_HI). Specifies, in multiples of
64 bytes, the level at which flow control will trigger. When this limit is
reached the chip will apply back pressure or will transmit a pause frame as
programmed in bits [3:0] of this register.
During full-duplex operation only a single pause frame is transmitted when
this level is reached. The pause time transmitted in this frame is
programmed in the FCPT field of the FLOW register in the MAC CSR space.
During half-duplex operation each incoming frame that matches the criteria
in bits [3:0] of this register will be jammed for the period set in the
BACK_DUR field.
Automatic Flow Control Low Level (AFC_LO). Specifies, in multiples of
64 bytes, the level at which a pause frame is transmitted with a pause time
setting of zero. When the amount of data in the RX data FIFO falls below
this level the pause frame is transmitted. A pause time value of zero
instructs the other transmitting device to immediately resume transmission.
The zero time pause frame will only be transmitted if the RX data FIFO had
reached the AFC_HI level and a pause frame was sent. A zero pause time
frame is sent whenever automatic flow control in enabled in bits [3:0] of this
register.
Note:
Backpressure Duration (BACK_DUR). When the LAN9211 automatically
asserts back pressure, it will be asserted for this period of time. This field
has no function and is not used in full-duplex mode. Please refer to
Table
information.
Flow Control on Multicast Frame (FCMULT). When this bit is set, the
LAN9211 will assert back pressure when the AFC level is reached and a
multicast frame is received. This field has no function in full-duplex mode.
Flow Control on Broadcast Frame (FCBRD). When this bit is set, the
LAN9211 will assert back pressure when the AFC level is reached and a
broadcast frame is received. This field has no function in full-duplex mode.
Flow Control on Address Decode (FCADD). When this bit is set, the
LAN9211 will assert back pressure when the AFC level is reached and a
frame addressed to the LAN9211 is received. This field has no function in
full-duplex mode.
AFC_CFG – Automatic Flow Control Configuration Register
This register configures the mechanism that controls both the automatic, and software-initiated
transmission of pause frames and back pressure.
Note: The LAN9211 will not transmit pause frames or assert back pressure if the transmitter is
5.5, describing Backpressure Duration bit mapping for more
Offset:
When automatic flow control is enabled the AFC_LO setting must
always be less than the AFC_HI setting.
disabled.
DESCRIPTION
ACh
DATASHEET
99
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 2.7 (03-15-10)
DEFAULT
00h
00h
0h
0
0
0
-